Method of forming a step pattern structure
US-9048193-B2 · Jun 2, 2015 · US
US9741563B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9741563-B2 |
| Application number | US-201615008328-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 27, 2016 |
| Priority date | Jan 27, 2016 |
| Publication date | Aug 22, 2017 |
| Grant date | Aug 22, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method for forming a stair-step structure in a substrate is provided, wherein the substrate has an organic mask, comprising at least one cycle, wherein each cycle comprises a) depositing a hardmask over the organic mask, b) trimming the organic mask, c) etching the substrate, d) trimming the organic mask, wherein there is no depositing a hardmask between etching the substrate and trimming the organic mask, e) etching the substrate, and f) repeating steps a-e a plurality of times forming the stair-step structure.
Opening claim text (preview).
What is claimed is: 1. A method for forming a stair-step structure in a substrate in a plasma processing chamber, wherein the substrate has an organic mask, comprising at least one cycle, wherein each cycle comprises: a) depositing a hardmask over the organic mask; b) trimming the organic mask; c) etching the substrate; d) trimming the organic mask, wherein there is no depositing a hardmask between etching the substrate and trimming the organic mask; and e) etching the substrate. 2. The method, as recited in claim 1 , further comprising repeating steps a-e a plurality of times forming the stair-step structure. 3. The method, as recited in claim 2 , wherein steps d and e are cyclically repeated at least once for each cycle of steps a-e. 4. The method, as recited in claim 3 , wherein each cycle of steps a-e is repeated at least 5 times. 5. The method, as recited in claim 4 , wherein the depositing the hardmask deposits hardmask on sidewalls of the organic mask further comprising trimming the hardmask between steps a and b. 6. The method, as recited in claim 5 , wherein the organic mask is a photoresist mask. 7. The method, as recited in claim 6 , wherein steps a-e are performed in a single plasma processing chamber. 8. The method, as recited in claim 7 , wherein the substrate comprises a plurality of layers, wherein each layer comprises at least two sublayers. 9. The method, as recited in claim 8 , wherein at least one of the at least two sublayers is a silicon oxide containing layer. 10. The method, as recited in claim 1 , wherein the depositing the hardmask deposits a top layer on top of the organic mask and a sidewall on the side of the organic mask and wherein the top layer of the hardmask has a thickness that is thicker than a thickness of the sidewall of the hardmask and further comprising trimming the hardmask between steps a and b. 11. The method, as recited in claim 1 , wherein step d smoothes the organic mask. 12. The method, as recited in claim 1 , wherein step c completely removes the hardmask, and wherein steps d and e are performed without a hardmask, and wherein step d partially etches the organic mask. 13. A method for making a three dimensional memory structure from a memory stack comprising a plurality of layers, wherein each layer comprises at least two sublayers and wherein an organic mask is over the memory stack, comprising: a) depositing a hardmask over a top of the organic mask; b) trimming the organic mask; c) etching the memory stack, so that portions of the memory stack not covered by the organic mask are etched a depth of the thickness of at least one layer of the plurality of layers; d) trimming the organic mask, wherein there is no depositing a hardmask between steps c and d; e) etching the memory stack; and f) repeating steps a-e a plurality of times forming the three dimensional memory structure. 14. The method, as recited in claim 13 , further comprising cyclically repeating steps d and e at least once before performing step f. 15. The method, as recited in claim 13 , wherein the depositing the hardmask deposits a sidewall layer on a sidewall of the organic mask, further comprising removing the sidewall layer of the hardmask. 16. The method, as recited in claim 15 , wherein a thickness of the top layer of the hardmask is greater than a thickness of the sidewall layer of the hardmask. 17. The method, as recited in claim 16 , wherein the organic mask is a photoresist mask. 18. The method, as recited in claim 17 , wherein steps a-f are performed in a single plasma processing chamber.
the material being a silicon oxide, e.g. SiO2 · CPC title
in the presence of a plasma [PECVD] · CPC title
characterised by the processes involved to create the masks · CPC title
Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title
characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.