Facilitating transaction completion subsequent to repeated aborts of the transaction

Patent metadata

Field	Value
Publication number	US-9740549-B2
Application number	US-201213524857-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

First claim

What is claimed is:

1. A computer program product for facilitating processing within a computing environment, said computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
tracking, by a processor of the computing environment, a number of times a transaction executing within the processor aborts, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and the tracking employing a counter within the processor to track the number of aborts of the transaction;
determining whether the transaction has successfully completed, and based on the transaction successfully completing, automatically resetting the counter to a predefined value;
based on the transaction aborting, automatically resetting the counter to the predefined value based on an interruption action, wherein the automatically resetting the counter to the predefined value is based on one of the following:
reaching by the counter a threshold number of aborts for the transaction causing an interrupt to be presented for the transaction, the counter to track the number of aborts of the transaction;
determining the abort of the transaction is due to an interruption; and

based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, re-executing the transaction via a transaction begin instruction.

2. The computer program product of claim 1 , wherein the transaction is a constrained transaction having a plurality of restrictions associated therewith, and wherein the transaction begin instruction is a transaction begin constrained instruction.

3. The computer program product of claim 1 , wherein the method further comprises based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, incrementing the counter, and setting a program instruction address to the transaction begin instruction to re-execute the transaction.

4. The computer program product of claim 1 , wherein the method further comprises based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, determining whether an action is to be taken to facilitate successful completion of the transaction on re-execution.

5. The computer program product of claim 4 , wherein the method further comprises:
selecting one or more actions based on the determining indicating an action is to be performed; and
performing the selected one or more actions.

6. The computer program product of claim 5 , wherein the one or more actions comprise one or more actions of the following actions: disabling branch prediction, disabling speculative instruction fetching, disabling super-scalar dispatching, disabling out-of-order execution, fetching cache misses exclusively, or executing a single instruction through an instruction pipeline.

7. The computer program product of claim 6 , wherein the following actions further comprise using a semaphore to block out one or more other processors.

8. The computer program product of claim 5 , wherein the selecting comprises choosing an action based on one or more of a value of the counter and a reason for the abort.

9. The computer program product of claim 1 , wherein the counter is a hardware counter.

10. A computer system for facilitating processing within a computing environment, said computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
tracking, by a processor of the computing environment, a number of times a transaction executing within the processor aborts, the transaction effectively delaying committing transactional stores to main memory until completion of a selected transaction, and the tracking employing a counter within the processor to track the number of aborts of the transaction;
determining whether the transaction has successfully completed, and based on the transaction successfully completing, automatically resetting the counter to a predefined value;
based on the transaction aborting, automatically resetting the counter to the predefined value based on an interruption action, wherein the automatically resetting the counter to the predefined value is based on one of the following:
reaching by the counter a threshold number of aborts for the transaction causing an interrupt to be presented for the transaction, the counter to track the number of aborts of the transaction;
determining the abort of the transaction is due to an interruption; and

based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, re-executing the transaction via a transaction begin instruction.

11. The computer system of claim 10 , wherein the transaction is a constrained transaction having a plurality of restrictions associated therewith, and the transaction begin instruction is a transaction begin constrained instruction.

12. The computer system of claim 10 , wherein the method further comprises based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, incrementing the counter, and setting a program instruction address to the transaction begin instruction to re-execute the transaction.

13. The computer system of claim 10 , wherein the method further comprises based on the transaction aborting for a reason other than an interruption, determining whether the counter has reached the threshold number of aborts, and based on the counter not reaching the threshold number of aborts, determining whether an action is to be taken to facilitate successful completion of the transaction on re-execution.

14. The computer system of claim 13 , wherein the method further comprises:
selecting one or more actions based on the determining indicating an action is to be performed; and
performing the selected one or more actions.

15. The computer system of claim 14 , wherein the one or more actions comprise one or more actions of the following actions: disabling branch prediction, disabling speculative instruction fetching, disabling super-scalar dispatching, disabling out-of-order execution, fetching cache misses exclusively, or executing a single instruction through an instruction pipeline.

16. The computer system of claim 15 , wherein the following actions further comprise using a semaphore to block out one or more other processors.

17. The computer system of claim 14 , wherein the selecting comprises choosing an action based on one or more of a value of the counter and a reason for the abort.

18. The computer system of claim 10 , wherein the counter is a hardware counter.

Assignees

• Belmar Brenton F
• Jacobi Christian
• Philley Randall W
• Slegel Timothy J
• IBM

Inventors

• Belmar Brenton F
• Jacobi Christian
• Philley Randall W
• Slegel Timothy J

Classifications

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F17/30371

  Physics · mapped topic

• G06F9/466 Primary

  Transaction processing · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title