Transaction abort instruction

Patent metadata

Field	Value
Publication number	US-2016350128-A1
Application number	US-201615232271-A
Country	US
Kind code	A1
Filing date	Aug 9, 2016
Priority date	Jun 15, 2012
Publication date	Dec 1, 2016
Grant date	—

Abstract

A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

First claim

What is claimed is:

1 . A computer program product for executing an instruction within a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining a machine instruction for execution, the machine instruction having associated therewith:
an operation code to specify a transaction abort operation; and
at least one field to be used to create an address, the address being an abort code; and

executing the machine instruction, the executing comprising:
aborting a transaction that is executing, wherein the transaction ends prior to completion; and
based on the aborting, providing a condition code, the condition code to indicate whether re-execution of the transaction is recommended, and wherein the condition code is based on the abort code.

2 . The computer program product of claim 1 , wherein the machine instruction has associated therewith a base field, and wherein based on the base field being zero, the at least one field includes a displacement field, and wherein a value of the displacement field specifies the abort code.

3 . The computer program product of claim 2 , wherein based on the base field being nonzero, the displacement field and the base field are used to create the abort code.

4 . The computer program product of claim 1 , wherein the abort code provides a user-defined specific reason for aborting, and wherein the machine instruction is a transaction abort instruction obtained from a program address specified by a machine program status word (PSW).

5 . The computer program product of claim 4 , wherein the method further comprises:
subsequent to executing the machine instruction, replacing the program address of the machine PSW with another program address obtained from a separate and distinct transaction PSW; and continuing execution of instructions beginning with an instruction at the other program address of the machine PSW.

6 . The computer program product of claim 1 , wherein the condition code comprises a first value based on a specified bit of the abort code being one value, and a second value based on the specified bit being another value.

7 . The computer program product of claim 6 , wherein the first value indicates re-execution is recommended and the second value indicates re-execution is not recommended.

8 . The computer program product of claim 1 , wherein the method further comprises placing the abort code in a transaction diagnostic block.

9 . The computer program product of claim 8 , wherein the transaction diagnostic block is specified by one of an instruction that initiated the transaction being aborted, or an instruction that initiated another transaction, in which the transaction and the other transaction are nested.

10 . The computer program product of claim 1 , wherein the method further comprises based on aborting the transaction, committing to memory non-transactional store accesses and discarding transactional store accesses.

11 . A computer system for executing an instruction within a computing environment, said computer system comprising:
a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining a machine instruction for execution, the machine instruction having associated therewith:
an operation code to specify a transaction abort operation; and
at least one field to be used to create an address, the address being an abort code; and

executing the machine instruction, the executing comprising:
aborting a transaction that is executing, wherein the transaction ends prior to completion; and
based on the aborting, providing a condition code, the condition code to indicate whether re-execution of the transaction is recommended, and wherein the condition code is based on the abort code.

12 . The computer system of claim 11 , wherein the machine instruction has associated therewith a base field, and wherein based on the base field being zero, the at least one field to specify the abort code includes a displacement field, wherein a value of the displacement field specifies the abort code.

13 . The computer program product of claim 12 , wherein based on the base field being nonzero, the displacement field and the base field are used to create the abort code.

14 . The computer system of claim 11 , wherein the abort code provides a user-defined specific reason for aborting, and wherein the machine instruction is a transaction abort instruction obtained from a program address specified by a machine program status word (PSW).

15 . The computer system of claim 14 , wherein the method further comprises:
subsequent to executing the machine instruction, replacing the program address of the machine PSW with another program address obtained from a separate and distinct transaction PSW; and continuing execution of instructions beginning with an instruction at the other program address of the machine PSW.

16 . The computer system of claim 11 , wherein the condition code comprises a first value based on a specified bit of the abort code being one value, and a second value based on the specified bit being another value.

17 . The computer system of claim 16 , wherein the first value indicates re-execution is recommended and the second value indicates re-execution is not recommended.

18 . The computer system of claim 11 , wherein the method further comprises placing the abort code in a transaction diagnostic block.

19 . The computer system of claim 18 , wherein the transaction diagnostic block is specified by one of an instruction that initiated the transaction being aborted, or an instruction that initiated another transaction, in which the transaction and the other transaction are nested.

20 . The computer system of claim 11 , wherein the method further comprises based on aborting the transaction, committing to memory non-transactional store accesses and discarding transactional store accesses.

Assignees

• IBM

Inventors

• Greiner Dan F
• Jacobi Christian
• Mitran Marcel
• Slegel Timothy J

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title