Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

Patent metadata

Field	Value
Publication number	US-9740269-B1
Application number	US-201715498261-A
Country	US
Kind code	B1
Filing date	Apr 26, 2017
Priority date	Oct 14, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.

First claim

The invention claimed is:

1. An apparatus comprising:
a first semiconductor device including a first external terminal; and
a resistor coupled to the first external terminal of the first semiconductor device;
wherein the first semiconductor device comprises:
a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor; and
a first arbiter circuit configured to detect, responsive to a first calibration command, if the resistor is available for the first semiconductor device, the first arbiter circuit further configured to activate the first calibration circuit when the resistor is detected to be available for the first semiconductor device and keep the first calibration circuit deactivated irrespective of the first calibration command when the resistor is detected to be unavailable for the first semiconductor device.

2. The apparatus of claim 1 , wherein the first arbiter circuit is further configured to determine whether or not the token information is stored therein responsive to the first calibration command to detect if the resistor is available.

3. The apparatus of claim 2 , wherein the resistor is detected to be available for the first semiconductor device when the token information is stored in the first arbiter circuit and to be unavailable for the first semiconductor device when the token is not stored in the first arbiter circuit.

4. The apparatus of claim 1 , further comprising a second semiconductor device including a second external terminal;
wherein the resistor is coupled in common to the first external terminal of the first semiconductor device and the second external terminal of the second semiconductor device;
wherein the second semiconductor device comprises:
a second calibration circuit configured to perform, when activated, a second calibration operation based on the resistor; and
a second arbiter circuit configured to detect, responsive to a second calibration command, if the resistor is available for the second semiconductor device, the second arbiter circuit further configured to activate the second calibration circuit when the resistor is detected to be available and keep the second calibration circuit deactivated irrespective of the second calibration command when the resistor is detected to be unavailable for the second semiconductor device.

5. The apparatus of claim 4 , wherein the resistor is detected to be available for the first semiconductor device responsive to when token information is stored in the first arbiter, and wherein the first arbiter circuit is further configured to transfer the token information to the second arbiter when the first calibration operation is finished.

6. The apparatus of claim 5 , wherein the second arbiter circuit is further configured to detect that the resistor is available for the second semiconductor device responsive to the token information being transferred from the first arbiter circuit to the second arbiter.

7. The apparatus of claim 4 , wherein the first arbiter circuit is further configured to transfer the token information to the second arbiter when the first calibration command is not asserted to the first semiconductor device for a predetermined period of time.

8. The apparatus of claim 1 , wherein the first arbiter circuit is further configured to determine a first voltage level at the first external terminal responsive to the first calibration command to detect if the resistor is available for the first semiconductor device.

9. The apparatus of claim 8 , wherein the first arbiter circuit is further configured to detect that the resistor is unavailable for the first semiconductor device when the first voltage level at the first external terminal is determined to be out of a first voltage range.

10. The apparatus of claim 9 , wherein the first arbiter circuit is further configured to determine the first voltage level at the first external terminal again to detect whether or not the first voltage level at the first external terminal is in the first voltage range when the resistor is detected to be unavailable for the first semiconductor device.

11. The apparatus of claim 8 , wherein the first arbiter circuit is further configured to determine the first voltage level at the first external terminal a plurality of times to detect if the resistor is available.

12. The apparatus of claim 11 , wherein the first arbiter circuit is further configured to determine whether the first voltage level at the first external terminal is in a first voltage range, sink a current at the first external terminal if the first voltage level at the first external terminal is determined to be in the first voltage range and determine whether the first voltage level at the first external terminal is in a second voltage range wider than the first voltage range after sinking the current at the first external terminal to detect if the resistor is available for the first semiconductor device.

13. The apparatus of claim 12 , wherein the first arbiter circuit is further configured to detect the resistor being unavailable for the first semiconductor device when the first voltage level at the first external terminal is determined to be out of the second voltage range.

14. The apparatus of claim 13 , wherein the first arbiter circuit is further configured to determine the first voltage level at the first external terminal again to detect whether or not the first voltage level at the first external terminal is in the first voltage range when the first voltage level at the first external terminal is determined to be out of the first voltage range.

15. The apparatus of claim 14 , wherein the first arbiter circuit is further configured to determine whether the first voltage level at the first external terminal again to detect whether or not the first voltage level at the first external terminal is in the first voltage range when the first voltage level at the first external terminal is determined to be out of the second voltage range.

16. The apparatus of claim 8 , further comprising a second semiconductor device including a second external terminal coupled to the resistor;
wherein the second semiconductor device comprises:
a second calibration circuit configured to perform, when activated, a second calibration operation based on the resistor; and
a second arbiter circuit configured to detect, responsive to a second calibration command, if the resistor is available for the second semiconductor device, the second arbiter circuit further configured to activate the second calibration circuit when the resistor is detected to be available for the second semiconductor device and keep the second calibration circuit deactivated irrespective of the second calibration command when the resistor is detected to be unavailable for the second semiconductor device;
wherein the second arbiter circuit is further configured to determine a second voltage level at the second external terminal responsive to the second calibration command to detect if the resistor is available for the second semiconductor device.

17. The apparatus of claim 16 , wherein the first arbiter circuit is further configured to detect that the resistor is unavailable for the first semiconductor device when the first voltage level at the first external terminal is determined to be out of a first voltage range and the second arbiter circuit is further configured to detect that the resistor is unavailable when the second voltage level at the second external terminal is determined to be out of the first voltage range.

Assignees

• Micron Technology Inc

Inventors

• Tatapudi Suryanarayana
• Ayyapureddi Sujeet

Classifications

• G11C8/10

  Decoders · CPC title

• G06F1/3225 Primary

  of memory devices · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title