Overload detection and correction in delta-sigma analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-9735802-B1
Application number	US-201615367667-A
Country	US
Kind code	B1
Filing date	Dec 2, 2016
Priority date	Dec 2, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based ΔΣ ADC) includes a VCO-based quantizer that includes delay elements to provide VCO outputs based on an analog input signal and combining logic to combine the VCO outputs so as to provide quantized outputs. Detection logic detects saturation of the VCO-based quantizer based on the quantized outputs and at least a portion of the VCO outputs. The VCO-based ΔΣ ADC also includes correction logic to modify the quantized outputs and provide modified quantized outputs in response to the detection logic detecting the saturation of the VCO-based quantizer and to provide the quantized outputs unmodified in the absence of saturation being detected.

First claim

What is claimed is:

1. A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based ΔΣ ADC) comprising:
a VCO-based quantizer comprising
delay elements to provide VCO outputs based on an analog input signal; and
combining logic to combine the VCO outputs so as to provide quantized outputs;

detection logic to detect saturation of the VCO-based quantizer based on the quantized outputs and at least a portion of the VCO outputs; and
correction logic to modify the quantized outputs and provide modified quantized outputs in response to the detection logic detecting the saturation of the VCO-based quantizer and to provide the quantized outputs unmodified in the absence of saturation being detected.

2. The converter of claim 1 , wherein
the VCO-based quantizer comprises a plurality of N-stage ring oscillators, each ring oscillator comprising a series of the delay elements, where N is a positive odd integer denoting the number of the delay elements,
the input signal is a differential signal that provides a complimentary signal to each of the ring oscillators, and
the detection logic is configured to detect the saturation of the VCO-based quantizer as VCO wrapping in the ring oscillators.

3. The converter of claim 2 , wherein the detection logic comprises:
a transition detector to determine which delay element in one of the ring oscillators is in transition and to provide an output from the combining logic corresponding to the determined delay element in transition;
a high-element counter to determine a proportion of outputs of the combining logic that are in transition; and
a saturation detector to detect whether the VCO-based quantizer is in a high or low saturation state based on signals from the transition detector and the high-element counter.

4. The converter of claim 3 , wherein the transition detector comprises, for each delay element in the one of the ring oscillators, an XNOR gate and an AND gate.

5. The converter of claim 3 , wherein the saturation detector comprises saturation state detectors, the outputs of the saturation state detectors representing quantizer states of entering high saturation, leaving high saturation, entering low saturation, or leaving low saturation.

6. The converter of claim 3 , wherein the saturation detector comprises sequence detector logic that, based on the output of the transition detector, provides outputs representing whether the transition detector has detected a “low-high” transition sequence or a “high-low” transition sequence.

7. The converter of claim 1 , wherein the correction logic comprises, for each of the quantized outputs, an inverter, an AND gate, and an OR gate.

8. The converter of claim 1 , further comprising a feedback loop connected between outputs of the correction logic and an input to the converter, the feedback loop including a multi-bit digital-to-analog converter (DAC), the feedback loop to provide from the correction logic outputs to the DAC one of the unmodified or modified quantized outputs depending on whether the saturation of the VCO-based quantizer is detected.

9. The converter of claim 8 , wherein the feedback loop has a loop gain, the converter further comprising a differential integrator within the feedback loop to achieve a second-order integration.

10. The converter of claim 1 , wherein the converter has an order higher than one.

11. An integrated circuit chip comprising the converter of claim 1 , fabricated on a substrate within an area no greater than 0.06 mm 2 .

12. A method of converting an analog signal to a corresponding digital signal, the method comprising:
detecting, based on quantized outputs and at least a portion of VCO outputs of a VCO-based quantizer, VCO wrapping in the VCO-based quantizer, the quantized outputs being generated by combining the VCO outputs;
modifying the quantized outputs to enforce a constant minimum or maximum output in response to detecting the saturation of the VCO-based quantizer.

13. The method of claim 12 , wherein the VCO-based quantizer comprises a first VCO and a second VCO, each comprising a plurality of delay elements;
wherein the combining, for each of pair of the VCO outputs, further comprises combining an output of a given delay element in the first VCO and an output of an associated delay element in the second VCO to provide a corresponding one of the quantized outputs; and
wherein the detecting VCO wrapping comprises:
determining which delay element of the plurality of delay elements in the first VCO currently is in transition; and
reading the quantized output corresponding to the determined delay element that is currently in transition.

14. The method of claim 13 , wherein the detecting VCO wrapping further comprises:
determining a proportion of logical “high” combining logic outputs to logical “low” combining logic outputs.

15. The method of claim 14 , wherein the detecting VCO wrapping further comprises:
determining, based on the read combining logic output corresponding to the determined currently transitioning delay element and on the determined proportion of combining logic outputs, that the VCO-based quantizer is high saturated; or
determining, based on the read combining logic output corresponding to the determined currently transitioning delay element and on the determined proportion of combining logic outputs, that the VCO-based quantizer is low saturated.

16. The method of claim 15 , wherein the modifying comprises:
modifying the quantized outputs to enforce a constant maximum output based on the determining that the VCO-based quantizer is high saturated; or
modifying the quantized outputs to enforce a constant minimum output based on the determining that the VCO-based quantizer is low saturated.

17. An analog-to-digital converter (ADC) comprising:
a quantizer comprising at least two ring oscillators arranged in a pseudo-differential manner, each ring oscillator comprising a plurality of delay elements, the quantizer having high and low saturation states characterized by phase differences between each of the ring oscillators;
an array of XOR gates, each XOR gate in the array to provide an output based on inputs from a corresponding delay element in each ring oscillator;
a feedback loop that includes a digital-to-analog converter (DAC); and
saturation correction logic arranged between the XOR gates and the DAC to enforce a constant maximum output signal or a constant minimum output signal for high and low saturation states, respectively, in response to detecting VCO wrapping between the at least two ring oscillators in the quantizer.

18. The converter of claim 17 , wherein the converter does not include components for dynamic element matching (DEM) of DAC elements.

19. The converter of claim 17 , further comprising detection logic to detect the VCO wrapping, the detection logic comprising:
a transition detector to determine which delay element in one of the at least two ring oscillators is in transition and to provide an output from the array of XOR gates corresponding to the determined delay element in transition;
a high-element counter to determine a proportion of outputs of the combining logic that are in transition; and
a saturation detector to detect whether the VCO-based quantizer is in a high or low saturation state based on signals from the transition detector and the high-element counter.

20. The converter of claim 17 , further comprising a differential integrator in the feedback loop to provide second-order or highe

Assignees

• Texas Instruments Inc

Inventors

• Marienborg Jan-Tore
• Edström Tobias

Classifications

• H03M1/1009

  Calibration · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/0617

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M3/422 Primary

  having one quantiser only · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title