Reducing switching error in data converters

Patent metadata

Field	Value
Publication number	US-9543974-B1
Application number	US-201514858239-A
Country	US
Kind code	B1
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

In some converter architectures, unary digital-to-analog (DAC) converter elements generate an analog output which represents the digital input signal. Thermometer codes trigger an appropriate number of DAC elements to generate the analog output. The DAC elements are not all perfectly weighted, and mismatch shaping is often used to dynamically equalize the usage of each DAC element during data conversion to average out the mismatches. Unfortunately, mismatch shaping adds additional switching and can worsen the effect of switching errors. Switching errors which are non-linearly dependent on the input causes a second order distortion if the sum of the switching errors corresponding to a set of DAC elements is not zero. Prior to data conversion, calibration can select a subset of DAC elements having a lesser sum of switching errors for data conversion. Other (redundant) DAC elements are not used at all or shut off permanently.

First claim

What is claimed is:

1. A method for reducing effect of switching errors, the method comprising:
determining, by an error measuring circuit, switching errors corresponding to digital-to-analog converter (DAC) elements in a converter;
determining, by an optimizer, a subset of DAC elements having a lesser sum of switching errors than one or more other possible subsets of DAC elements; and
calibrating, using control logic, the converter by selecting the subset of DAC elements for data conversion.

2. The method of claim 1 , wherein the switching errors are independent from switching direction.

3. The method of claim 1 , wherein the switching errors cause a second order distortion if a sum of the switching errors is not zero.

4. The method of claim 1 , further comprising:
permanently turning off one or more DAC elements which are not in the subset of DAC elements.

5. The method of claim 1 , wherein the calibrating of the converter comprises:
outputting, by the control logic, control signals to a plurality of switches; and
controlling states of the switches to route input signals to only the subset of DAC elements for data conversion.

6. The method of claim 1 , wherein the determining of the subset of DAC elements having the lesser sum of switching error comprises:
determining sums of switching error corresponding to a plurality of possible subsets of DAC elements.

7. The method of claim 6 , wherein the determining of the subset of DAC elements having the lesser sum of switching error further comprises:
selecting the subset of DAC elements having the least sum of switching error.

8. The method of claim 1 , wherein:
the converter further comprises comparators and the outputs of the comparators drive respective DAC elements; and
the determining of the subset of DAC elements comprises determining the subset of DAC elements having the lesser sum of switching error, wherein the subset of DAC elements are driven by a subset of comparators.

9. The method of claim 8 , wherein the calibrating the converter comprises:
outputting, by the control logic, control signals to a plurality of switches; and
controlling states of the switches to route reference voltages to only the subset of comparators of the converter whose outputs drive the subset of DAC elements for data conversion.

10. The method of claim 8 , wherein the determining of the subset of DAC elements comprises:
determining sums of switching error corresponding to a plurality of possible subsets of DAC elements driven by corresponding comparators.

11. Circuitry for reducing switching errors, the circuitry comprising:
an error measuring circuit for measuring average output of the digital-to-analog (DAC) elements in a converter while toggling one DAC element at a time to determine switching errors corresponding to DAC elements;
an optimizer for determining a subset of DAC elements having a lesser sum of switching errors than one or more other possible subsets of DAC elements; and
control logic for calibrating the converter by selecting the subset of DAC elements for data conversion.

12. The circuitry of claim 11 , further comprising:
a signal generator generating one or more inputs to the converter for toggling an output of one DAC element at a time at different toggling frequencies while keeping outputs of the rest of the DAC elements fixed.

13. The circuitry of claim 11 , wherein the control logic outputs control signals to an N to M mapping matrix of switches, wherein N is a number of elements in the subset of DAC elements and M is a number of available DAC elements.

14. The circuitry of claim 11 , wherein the control logic outputs control signals to a plurality of 1 to M−N+1 demultiplexers, wherein N is a number of elements in the subset of DAC elements and M is a number of available DAC elements.

15. The circuitry of claim 11 , wherein the control logic outputs control signals to a plurality of 1 to 2 demultiplexers.

16. The circuitry of claim 11 , wherein:
the control logic is configured to output control signals to a plurality of switches to route input signals to only a subset of DAC elements for conversion.

17. The circuitry of claim 11 , wherein:
the control logic is configured to output control signals to a plurality of switches to route reference voltages to only a subset of comparators of the converter, wherein outputs of the subset of comparators drive the subset of DAC elements.

18. A data converter with reduction of switching error worsened by dynamic element matching, the data converter comprising:
digital-to-analog converter (DAC) elements comprising one or more redundant DAC elements;
an error measuring circuit for determining switching errors corresponding to the DAC elements;
an optimizer for determining a subset of DAC elements having a lesser sum of switching errors than one or more other possible subsets of DAC elements; and
control logic for calibrating the data converter by selecting the subset of DAC elements for data conversion.

19. The data converter of claim 18 , further comprises:
a mismatch shaping encoder for equalizing usage of the subset of DAC elements during data conversion.

20. The data converter of claim 18 , further comprising:
comparators for comparing an analog input to different reference voltages and outputs of the comparators drive the DAC elements to reconstruct the analog input;
wherein the control logic is configured to output control signals to a plurality of switches to route reference voltages to only a subset of comparators of the converter, wherein outputs of the subset of comparators drive the subset of DAC elements.

21. The method of claim 1 , wherein the DAC elements are unary weighted, and usage of the subset of DAC elements for data conversion are substantially equalized by a switching scheme.

22. The method of claim 1 , wherein the switching errors are non-linearly dependent on the input to the DAC elements.

23. The method of claim 1 , further comprising:
generating one or more inputs to the converter for toggling an output of one DAC element at a time at different toggling frequencies while keeping outputs of the rest of the DAC elements fixed.

24. The method of claim 23 , further comprising:
measuring average outputs of the DAC elements for different toggling frequencies.

25. The method of claim 24 , wherein the determining of the switching errors comprises:
characterizing a switching error based on at least two different average outputs corresponding to different toggling frequencies.

26. The method of claim 1 , wherein the determining of the switching errors comprises using a pilot tone as an input to the converter and solving for switching errors corresponding to the DAC elements based on an observed output.

27. The method of claim 26 , wherein the pilot tone is a sinewave.

28. The circuitry of claim 11 , wherein the DAC elements are unary weighted, and usage of the subset of DAC elements for data conversion are substantially equalized by a switching scheme.

29. The circuitry of claim 11 , wherein the switching errors are non-linearly dependent on the input to the DAC elements.

30. The data converter of claim 18 , wherein the DAC elements are unary weighted.

31. The data converter of claim 18 , wherein the switching errors are non-linearly depe

Assignees

• Analog Devices Inc

Inventors

• Yang Wenhua W

Classifications

• H03M1/662

  Multiplexed conversion systems · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/066 Primary

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title

• H03M1/1033

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title