Jitter-based clock selection

Patent metadata

Field	Value
Publication number	US-9735791-B2
Application number	US-201615130802-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Jul 1, 2011
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

First claim

What is claimed is:

1. A method of operation within an integrated circuit device, the method comprising:
generating a plurality of clock signals within respective oscillators in response to an input clock signal;
determining respective measures corresponding to clock jitter for the clock signals;
selecting, based at least in part on the measures corresponding to clock jitter, a preferred one of the clock signals; and
outputting the preferred one of the clock signals as an output clock signal.

2. The method of claim 1 further comprising determining, for each of the plurality of clock signals, whether the clock signal is oscillating at an integer multiple of the frequency of the input clock signal.

3. The method of claim 2 wherein selecting the preferred one of the clock signals comprises excluding from selection as the preferred one of the clock signals any of the plurality of clock signals determined not to be oscillating at an integer multiple of the frequency of the input clock signal.

4. The method of claim 2 wherein the integer multiple is one or higher.

5. The method of claim 1 wherein generating the plurality of clock signals within respective oscillators comprises generating the plurality of clock signals within respective injection-locked oscillators.

6. The method of claim 5 wherein generating the plurality of clock signals within respective injection-locked oscillators comprises generating at least two or more of the plurality of clock signals at frequencies that are integer multiples of the frequency of the input clock signal, each of the integer multiples being one or higher.

7. The method of claim 5 wherein generating the plurality of clock signals within respective injection-locked oscillators comprises generating the plurality of clock signals within injection-locked oscillators that have respective natural frequencies that are offset from one another.

8. The method of claim 7 further comprising tuning the injection-locked oscillators to the respective natural frequencies that are offset from one another.

9. The method of claim 8 wherein the injection-locked oscillators are capable of injection-locking to respective individual ranges of input clock frequencies, and wherein tuning the injection-locked oscillators to respective natural frequencies that are offset from one another comprises spectrally staggering the individual ranges of input clock frequencies.

10. The method of claim 1 wherein determining respective measures corresponding to clock jitter for the clock signal comprises determining respective clock jitter magnitudes corresponding to the clock signals, and wherein selecting the preferred one of the clock signals comprises determining which of the clock jitter magnitudes is lowest and selecting whichever of the plurality of clock signals corresponds to the lowest of the clock jitter magnitudes.

11. The method of claim 1 wherein generating the respective measures corresponding to clock jitter comprises generating a respective value indicative of edge-to-edge timing variation for each of the clock signals.

12. An integrated circuit device comprising:
a plurality of oscillators to generate respective clock signals in response to an input clock signal;
jitter determination circuitry to determine respective measures corresponding to clock jitter for the clock signals; and
selection circuitry to select, based at least in part on the measures corresponding to clock jitter, a preferred one of the clock signals to be an output clock signal.

13. The integrated circuit device of claim 12 further comprising frequency verification circuitry to determine, for each of the plurality of clock signals, whether the clock signal is oscillating at a respective integer multiple of the frequency of the input clock signal, each respective integer multiple being one or higher.

14. The integrated circuit device of claim 13 wherein selection circuitry includes logic circuitry to exclude from selection as the output clock signal any of the plurality of clock signals determined by the frequency verification circuitry not to be oscillating at an integer multiple of the frequency of the input clock signal.

15. The integrated circuit device of claim 12 wherein the plurality of oscillators comprise injection-locked oscillators.

16. The integrated circuit device of claim 15 wherein the injection-locked oscillators comprise circuitry to generate the respective clock signals at frequencies that are an integer multiple of the frequency of the input clock signal, the integer multiple being one or higher.

17. The integrated circuit device of claim 15 wherein the injection-locked oscillators have respective natural frequencies that are offset from one another.

18. The integrated circuit device of claim 17 further comprising calibration circuitry to tune the injection-locked oscillators to respective natural frequencies that are offset from one another.

19. The integrated circuit device of claim 18 wherein the injection-locked oscillators are capable of injection-locking to respective individual ranges of input clock frequencies, and wherein the calibration circuitry to tune the injection-locked oscillators to respective natural frequencies that are offset from one another comprises circuitry to spectrally stagger the individual ranges of input clock frequencies.

20. The integrated circuit device of claim 12 wherein the jitter determination circuitry to determine respective measures corresponding to clock jitter for the clock signals comprises circuitry to determine respective clock jitter magnitudes corresponding to the clock signals, and wherein the selection circuitry comprises circuitry to determine which of the clock jitter magnitudes is lowest and to select, as the preferred one of the clock signals, whichever of the plurality of clock signals corresponds to the lowest of the clock jitter magnitudes.

21. The integrated circuit device of claim 12 wherein the jitter determination circuitry to generate the respective measures corresponding to clock jitter comprises circuitry to generate a respective value indicative of edge-to-edge timing variation for each of the clock signals.

22. A non-transitory machine readable medium that stores data representative of a circuit component comprising:
a plurality of oscillators to generate respective clock signals in response to an input clock signal;
jitter determination circuitry to determine respective measures corresponding to clock jitter for the clock signals; and
selection circuitry to select, based at least in part on the measures corresponding to clock jitter, a preferred one of the clock signals to be an output clock signal.

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Leibowitz Brian S
• Hossain Masum

Classifications

• H03L7/06 Primary

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title