Method and apparatuses for optimizing power management on an integrated circuit device

Patent metadata

Field	Value
Publication number	US-9735778-B1
Application number	US-201414464588-A
Country	US
Kind code	B1
Filing date	Aug 20, 2014
Priority date	Aug 20, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Input-output (IO) circuitry for optimizing power management on an integrated circuit is disclosed. The IO circuitry includes monitoring circuitry and a multiplexer circuit that is controlled by the monitoring circuitry. The monitoring circuitry determines whether majority of the bits of an IO signal are transitioning from a first logical state to a second logical state. When a number of bit transitions of the IO signal exceeds a predetermined bit transition threshold, the monitoring circuitry may send a monitoring circuitry output to the multiplexer circuit to selectively couple an output signal to either the IO signal or an inverted IO signal. The IO circuitry further includes an additional multiplexer that receives the monitoring circuitry output and a clock signal. The additional multiplexer selects an additional output signal from the monitoring circuitry output and the clock signal based on a control signal that indicates a power-savings operation.

First claim

What is claimed is:

1. Input-output (IO) circuitry, comprising:
monitoring circuitry that determines whether a predetermined threshold number of bits of an IO signal are transitioning from a first logical state to a second logical state;
an encoder circuit that generates an encoded IO signal in response to the monitoring circuitry indicating that the number of bits of the IO signal that are transitioning from the first logical state to the second logical state exceeds the predetermined threshold number, wherein transmitting the encoded IO signal requires less power than transmitting the IO signal; and
an output port of the IO circuitry that outputs a clock signal in a first mode of the IO circuitry and that outputs an additional IO signal bit that is associated with the encoded IO signal in a second mode of the IO circuitry.

2. The IO circuitry defined in claim 1 , wherein the encoder circuit further comprising:
a multiplexer circuit that receives the IO signal and an inverted IO signal, wherein the multiplexer circuit is controlled by the monitoring circuitry to selectively couple an output signal to either the IO signal or the inverted IO signal.

3. The IO circuitry defined in claim 2 , wherein the predetermined threshold number is half the number of bits in the IO signal, the monitoring circuitry further comprising:
circuitry for generating a monitoring circuitry output when the number of bit transitions exceeds half the number of bits in the IO signal; and
circuitry for selectively coupling the output signal to the inverted IO signal when the monitoring circuitry output indicates that the number of bit transitions exceeds half the number of bits in the IO signal.

4. The IO circuitry defined in claim 3 further comprising:
an additional multiplexer circuit that receives the monitoring circuitry output and a clock signal.

5. The IO circuitry defined in claim 4 further comprising:
a control circuit that activates the monitoring circuitry using a control signal, wherein the control signal is indicative of a power-savings operation.

6. The IO circuitry defined in claim 5 , wherein the control circuit sends the control signal to the additional multiplexer circuit to select an output signal from the monitoring circuitry output and the clock signal.

7. Input-output (IO) circuitry, comprising:
a control circuit that produces a control signal, wherein the control signal is indicative of a power-savings operation; and
an encoder circuit that receives the IO signal and that has an enabled mode and a disabled mode, wherein the encoder circuit selectively generates an encoded IO signal in response to the control signal having a first value indicating a power-savings operation in the enabled mode, wherein the encoder circuit is disabled in response to the control signal having a second value in the disabled mode, and wherein the encoder circuit comprises:
multiplexer circuitry that receives the IO signal and an inverted IO signal, wherein the multiplexer circuitry is controlled by the control circuit to selectively couple an output signal to either the IO signal or the inverted IO signal.

8. The IO circuitry defined in claim 7 , wherein further comprising:
a logic gate that receives the control signal an input bit signal, wherein the logic gate produces an enable signal based on at least the control signal and the input bit signal.

9. The IO circuitry defined in claim 8 , wherein the logic gate sends the enable signal to the multiplexer circuit to select the inverted IO signal as the output signal.

10. An integrated circuit, comprising:
an input-output (IO) block coupled to a plurality of IO pins, wherein the plurality of IO pins produce an IO signal; and
monitoring circuitry that receives a control bit at a pin in the IO block in a first mode of the integrated circuit, and that receives a clock signal at the pin in a second mode of the integrated circuit, wherein the control bit indicates whether the IO signal is an inverted IO signal.

11. The integrated circuit defined in claim 10 , wherein the monitoring circuitry compares the IO signal to a predetermined IO signal to determine whether a number of bit transitions in the IO signal exceeds a predetermined bit transition threshold during the power-savings operation, and further wherein the monitoring circuitry asserts a power reduction control signal when the number of bit transitions in the IO signal exceeds the predetermined bit transition threshold.

12. The integrated circuit defined in claim 11 , further comprising:
a multiplexer circuit having first and second input terminals, wherein the first input terminal receives the IO signal from the IO block and the second input terminal receives an inverted IO signal, wherein the power reduction control signal controls the multiplexer circuit to selectively couple an output signal to either the IO signal or the inverted IO signal.

13. The integrated circuit defined in claim 12 , further comprising:
an additional integrated circuit coupled to the integrated circuit, wherein the integrated circuit and the additional integrated circuit are mounted on an interposer, wherein the integrated circuit is placed adjacent to the additional integrated circuit, and wherein the additional integrated circuit receives the selected output signal from the integrated circuit.

14. The integrated circuit defined in claim 12 , further comprising:
an additional integrated circuit coupled to the integrated circuit via microbumps, wherein the integrated circuit and the additional integrated circuit are stacked on each other to form a stack structure, and wherein the additional integrated circuit receives the selected output signal from the integrated circuit.

15. The integrated circuit defined in claim 10 , further comprising:
a control circuit that provides a control signal to the monitoring circuitry over the pin, wherein the control signal activates the monitoring circuitry to perform a power -savings operation.

16. A method comprising:
with an input-output (IO) block coupled to a plurality of IO pins, producing an IO signal;
with control circuitry, initiating a power -savings operation by setting a control signal to a first value;
with monitoring circuitry, monitoring the power consumption associated with transmitting the IO signal monitoring switching activities of the plurality of bits of the IO signal; and
in response to the control signal having the first value, generating an encoded IO signal with an encoder circuit if the monitoring circuitry indicates that the majority of bits of the IO signal are transitioning from a first logical state to a second logical state, wherein transmitting the encoded IO signal requires lower power than transmitting the IO signal.

17. The method defined in claim 16 , wherein generating the encoded IO signal further comprises:
with a multiplexer circuit, receiving the IO signal and an inverted IO signal, wherein the multiplexer circuit is controlled by the monitoring circuitry to selectively couple an output signal to either the IO signal or the inverted IO signal.

18. The method defined in claim 17 , further comprising:
with a control circuit, controlling the monitoring circuitry to monitor the power consumption associated with the IO block using a control signal, wherein the control signal is indicative of a power-savings operation.

19. The method defined in claim 18 , wherein monitoring the switching activities of the plurality of IO pins comprises:
with the monitoring circuitry, comparing a number

Assignees

• Altera Corp

Inventors

• Schulz Jeffrey

Classifications

• H03K19/17744

  for input/output signals · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title