Multi-orientation integrated cell, in particular input/output cell of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9735772-B2
Application number	US-201514865618-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Nov 12, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

First claim

The invention claimed is:

1. An integrated circuit comprising:
at least one integrated cell disposed at a location of the integrated circuit;
a multiplexer coupled to at least one site of the integrated cell;
first and second integrated devices coupled to the multiplexer and respectively oriented in two directions of orientation, the first integrated device being usable because of the first integrated device's direction of orientation and the second integrated device being unusable because of the second integrated device's direction of orientation; and
a controller comprising two integrated test devices separate from the first and second integrated devices and respectively oriented in the two directions of orientation, the two integrated test devices being usable in each of the two directions of orientation, the controller being configured to detect a usability of the first integrated device and control the multiplexer to couple the first integrated device electrically to the at least one site.

2. The integrated circuit according to claim 1 , wherein the controller comprises:
a detection circuit having the two integrated test devices respectively oriented in the two directions of orientation, each integrated test device comprising an element exhibiting a characteristic according to the direction of orientation and representative of a usable or non-usable character of the first and second integrated devices; and
a detector configured to analyze the characteristic of the element of each of the two integrated test devices and to deliver a control signal to the multiplexer.

3. The integrated circuit according to claim 2 , wherein the characteristic of the element of each of the two integrated test devices comprises an electrical parameter.

4. The integrated circuit according to claim 1 , wherein the two directions of orientation are orthogonal.

5. The integrated circuit according to claim 1 , wherein the first and second integrated devices comprise thin gate oxide MOS transistors, a longitudinal direction of each gate defining a direction of orientation of each thin gate oxide MOS transistor.

6. The integrated circuit according to claim 5 , wherein each integrated test device comprises a thick gate oxide MOS transistor, a longitudinal direction of each gate defining a direction of orientation of the thick gate oxide MOS transistor, and the element comprises a doped zone having a part extending under the gate of the thick gate oxide MOS transistor, the characteristic being a dimension of the part measured in a direction of a length of a channel.

7. The integrated circuit according to claim 3 , wherein the electrical parameter comprises a threshold voltage of each integrated test device, and the detector is configured to detect one of the test integrated test devices which exhibits the highest threshold voltage, and to deliver the control signal to the multiplexer selecting the integrated device having the same direction of orientation as that of the integrated test device exhibiting the highest threshold voltage.

8. The integrated circuit according to claim 2 , wherein the element comprises a gate of each integrated test device, the characteristic being a roughness of the gate.

9. The integrated circuit according to claim 3 , wherein the electrical parameter comprises a leakage current of each integrated test device, and the detector is configured to detect one of the two integrated test devices which exhibits the smallest leakage current, and to deliver to the multiplexer a control signal selecting the integrated device having the same direction of orientation as that of the integrated test device exhibiting the smallest leakage current.

10. The integrated circuit according to claim 1 , wherein the at least one integrated cell comprises a plurality thereof arranged in a rectangular annulus defining input/output cells of the integrated circuit.

11. A method of fabricating an integrated circuit comprising at least one integrated cell disposed at a location of the integrated circuit, a multiplexer coupled to at least one site of the integrated cell, first and second integrated devices coupled to the multiplexer and respectively oriented in two directions of orientation, a controller to control the multiplexer, the first integrated device being usable because of its direction of orientation and the second integrated device being unusable because of its direction of orientation, the method comprising:
detecting the first integrated device; and
controlling, with the controller, the multiplexer to couple the first integrated device electrically to the at least one site, the controller comprising two integrated test devices separate from the first and second integrated devices and respectively oriented in the two directions of orientation, the two integrated test devices being usable in each of the two directions of orientation.

12. The method according to claim 11 , wherein the controller comprises a detection circuit having the two integrated test devices respectively oriented in the two directions of orientation, each integrated test device comprising an element exhibiting a characteristic according to the direction of orientation and representative of a usable or non-usable character of the first and second integrated devices.

13. The method according to claim 12 , wherein the characteristic of the element of each of the two integrated test devices comprises an electrical parameter.

14. The method according to claim 13 , wherein the two integrated test devices are different from the first integrated device and usable in the two directions of orientation.

15. The method according to claim 13 , further comprising:
detecting one of the test integrated test devices which exhibits the highest threshold voltage; and
delivering the control signal to the multiplexer selecting the integrated device having the same direction of orientation as that of the integrated test device exhibiting the highest threshold voltage.

16. An integrated circuit comprising:
at least one integrated cell having at least one site;
a multiplexer coupled to the at least one site;
first and second integrated devices coupled to the multiplexer and each oriented in a different direction of orientation, the first integrated device being operable because of the first integrated device's direction of orientation and the second integrated device being inoperable because of the second integrated device's direction of orientation; and
a controller coupled to the multiplexer and configured to couple one integrated device of the first and second integrated devices to the at least one site, the controller comprising,
two integrated test devices separate from the first and second integrated devices and respectively oriented in the two directions of orientation, the two integrated test devices being operable in each of the two directions of orientation, and
a detector coupled to the two integrated test devices and configured to detect which one of the two integrated test devices has a highest threshold voltage, and to transmit to the multiplexer a control signal selecting one of the first and second integrated devices having a same direction of orientation as that of the integrated test device having the highest threshold voltage.

17. The integrated circuit according to claim 16 , wherein each integrated test device comprises a thick gate oxide MOS transistor, a longitudinal direction of each gate defining a direction of orientation of the thick gate oxide MOS transistor.

Assignees

• St Microelectronics Sa
• St Microelectronics Crolles 2 Sas

Inventors

• Dray Alexandre
• Josse Emmanuel

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H01L27/0207

  Electricity · mapped topic