Vertical hall effect sensor

Patent metadata

Field	Value
Publication number	US-9735345-B2
Application number	US-201615060791-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Sep 30, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

First claim

What is claimed is:

1. A magnetic field sensing device comprising:
a plurality of vertical Hall effect sensors, each vertical Hall sensor comprising:
a plurality of semiconductor electrodes; and
a plurality of electrically floating semiconductor fingers interdigitated between the plurality of electrodes wherein the plurality of vertical Hall effect sensors is built within at least one surface of a semiconductor wafer and arranged in a circle, and

wherein each vertical Hall effect sensor is configured to measure the magnetic field in a direction radially inward to or outward from a center of the semiconductor wafer,
wherein the plurality of semiconductor electrodes comprising:
a source electrode;
a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the second sensing electrode; and
a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode; and

wherein the plurality of semiconductor fingers interdigitated with the plurality of semiconductor electrodes comprises a first semiconductor finger of the plurality of semiconductor fingers disposed between the source electrode and the first sensing electrode.

2. The sensing device of claim 1 , wherein the semiconductor fingers are between one-tenth and two-tenths of the thickness of the semiconductor wafer.

3. The sensing device of claim 1 , wherein the semiconductor wafer includes a retrograde dopant profile.

4. The sensing device of claim 1 , wherein the floating semiconductor fingers are electrically connected to one another.

5. The sensing device of claim 1 , wherein the plurality of semiconductor fingers interdigitated with the plurality of semiconductor electrodes further comprises a second semiconductor finger of the plurality of semiconductor fingers disposed between the source electrode and the second sensing electrode.

6. A method comprising:
fabricating a vertical Hall effect sensor comprising:
forming an epitaxial layer of a semiconductor with a first conductivity type on a semiconductor substrate with a second conductivity type;
selectively doping at least five electrodes with the first conductivity type on a surface of the epitaxial layer;
selectively doping at least four semiconductor fingers that are interdigitated with the at least five electrodes, the at least four semiconductor fingers having the second conductivity type, wherein the at least four semiconductor fingers interdigitated with the at least five electrodes comprises a first semiconductor finger of the at least semiconductor five fingers disposed between a source electrode and a first sensing electrode of the at least five electrodes; and
selectively doping at least one blanket region with the first conductivity type within the epitaxial layer.

7. The method of claim 6 , wherein selectively doping at least one blanket region within the epitaxial layer further comprises depositing an N-type dopant only along a preferred current path through the semiconductor substrate.

8. The method of claim 7 , wherein the N-type dopant is phosphorous.

9. The method of claim 6 , wherein the blanket region has a higher charge carrier density than the epitaxial layer.

10. The method of claim 6 , wherein selectively doping at least four semiconductor fingers further comprises:
depositing a P-type dopant only along a preferred region between any two N-type electrodes using a mask.

11. The method of claim 6 , wherein forming the epitaxial layer of the semiconductor with the first conductivity type on the semiconductor substrate with the second conductivity type further comprises modifying a dopant level during epitaxial deposition in order to form a retrograde dopant profile.

12. The method of claim 6 , further comprising electrically connecting the semiconductor fingers to each other.

13. The method of claim 6 , further comprising electrically insulating the semiconductor fingers from one another.

Assignees

• Allegro Microsystems Llc

Inventors

• Kosier Steven
• Hoilien Noel

Classifications

• H01L27/22

  Electricity · mapped topic

• G01R33/077 Primary

  Vertical Hall-effect devices · CPC title

• H01L43/065 Primary

  Electricity · mapped topic

• H01L43/04

  Electricity · mapped topic

• H01L43/14

  Electricity · mapped topic