Fabrication of IGZO oxide TFT on high CTE, low retardation polymer films for LDC-TFT applications

Patent metadata

Field	Value
Publication number	US-9735283-B2
Application number	US-201415023770-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Sep 27, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

The present invention provides a TFT on a polymer substrate and a method for producing the TFT. The TFT is, due to its characteristics, particularly suited for applications as backplane in LCD displays and solar cell devices.

First claim

The invention claimed is:

1. A thin film transistor on a polymer substrate, comprising:
a gate electrode;
a gate insulating film covered by the gate electrode, the gate insulating film comprising methylsiloxane having a methyl content in the range of from ≧1 wt.-% to ≦13 wt.-%;
a semiconductor channel layer placed to face the gate electrode with the gate insulating film interposed there between, the semiconductor channel layer comprising at least one of a metal oxide semiconductor including an oxide of at least one of Hf, In, Ga, or Zn and mixtures thereof;
a source drain pattern comprising a source electrode connected to the semiconductor layer and a drain electrode separated from the source electrode and connected to the semiconductor layer,
wherein the semiconductor layer has a source portion that contacts the source electrode, a drain portion that contacts the drain electrode, and a channel portion that is located between the source and drain portions;
wherein the gate electrode and the source and gate electrodes comprise at least one of Al, Ti, Mo, AlNd, a stack metal electrode Ti/Al/Ti, or a transparent conducting oxide selected from the group consisting of indium tin oxide, indium doped zinc oxide, aluminum doped zinc oxide, fluorine tin oxide, antimony tin oxide, and mixtures thereof;
a polymer substrate comprising a thermoplastic polymer film.

2. The thin film transistor according to claim 1 , wherein polymer substrate further comprises a planarized hard coat layer on at least one side of the thermoplastic polymer film, and wherein the planarized hard coat layer comprises a UV cured acrylate or a thermally cured planarizier.

3. The thin film transistor according to claim 1 , wherein the thermoplastic polymer film of polymer substrate comprises polycarbonates, polyethylene terephthalate, polyurethane, polyetherketones, polyethylene, polystyrene, polyvinylalcohole, epoxide resins or polyamides, wherein the thermoplastic polymer film has a T g of at least 160° C.

4. The thin film transistor according to claim 2 , wherein the hard coat of the polymer substrate comprises ionization curing polyester acrylate and/or urethane acrylate.

5. The thin film transistor according to claim 1 , wherein the thermoplastic polymer film of polymer substrate comprises polycarbonate, wherein said polycarbonate is a high molecular weight, thermoplastic, aromatic polycarbonate with M w (weight average of the molecular weight) of at least 10 000, which comprise bifunctional carbonate structural units of formula (I),

wherein
R 1 and R 2 independently of one another are hydrogen or halogen,
m is an integer of from 4 to 7,
R 3 and R 4 is selected for each X individually and, independently of one another, is hydrogen or C 1 -C 6 alkyl and
X is carbon, and
n is an integer of 30 or greater,
with the proviso that, on at least one X atom, R 3 and R 4 simultaneously are alkyl.

6. The thin film transistor according to claim 5 , wherein the polycarbonate is a copolycarbonate having structural units of formula (I-h)

wherein the comonomers can be in an alternating, block or random arrangement in the copolymer, p+q=n and the ratio of q is such that the diphenols containing the spirocompound are contained in quantities of from 100 mole % to 2 mole %, based on the total quantity of 100 mole % of diphenol units, in polycarbonates.

7. The thin film transistor according to claim 2 , wherein the thermoplastic polymer film has a thickness in the range of from ≧50 μm to ≦350 μm and the hard coat has a thickness in the range of from ≧3 μm to ≦15 μm.

8. A method utilizing the thin film transistor according to claim 1 as TFT backplane for active matrix displays.

9. A method for producing a thin film transistor on a polymer substrate, the method comprising the steps of:
(a) laminating a polymer substrate comprising a thermoplastic polymer film onto a glass carrier;
(b) depositing a layer of aluminum oxide on the polymer substrate, thereby forming a barrier and adhesion layer;
(c) depositing gate electrode layer, the step comprising depositing a metal and/or metal oxide film and a subsequent photolithographic treatment;
(d) coating with methylsiloxane having a methyl content in the range of from ≧1 wt.-% to ≦13 wt.-%, and subsequent annealing at a lower temperature than T G of the polymer substrate, thereby forming the gate insulating film;
(e) depositing a metal and/or metal oxide film and carrying out a photolithographic treatment to form source drain pattern;
(f) depositing an oxide layer comprising at least one oxide of Hf, In, Ga or Zn to form semiconductor layer,
wherein the metal or metal oxide of (c) and (e) comprise at least one of Al, Ti, Mo, AlNd, a stack metal electrode Ti/Al/Ti, or a transparent conducting oxide selected from the group consisting of indium tin oxide, indium doped zinc oxide, aluminum doped zinc oxide, fluorine tin oxide, antimony tin oxide, and mixtures thereof.

10. The method according to claim 9 , wherein the thermoplastic polymer film of polymer substrate comprises polycarbonates, polyethylene terephthalate, polyurethane, polyetherketones, polyethylene, polystyrene, polyvinylalcohole, epoxide resins or polyamides, wherein the thermoplastic film has a T g of at least 160° C.

11. The method according to claim 9 , wherein the thermoplastic polymer film of polymer substrate comprises polycarbonate, wherein said polycarbonate is a high molecular weight, thermoplastic, aromatic polycarbonate with M w (weight average of the molecular weight) of at least 10 000, which contain bifunctional carbonate structural units of formula (I),

wherein
R 1 and R 2 independently of one another are hydrogen or halogen,
m is an integer of from 4 to 7,
R 3 and R 4 may be selected for each X individually and, independently of one another, and are hydrogen or C 1 -C 6 alkyl and
X is carbon, and
n is an integer of 30 or greater,
with the proviso that, on at least one X atom, R 3 and R 4 simultaneously are alkyl.

12. The method according to claim 9 , wherein the annealing in step d) is carried out over a time in the range of from ≧0.5 h to ≦10 h.

13. The method according to claim 9 , wherein the polymer substrate further comprises a planarized hard coat layer on at least one side of the thermoplastic polymer film, and wherein the planarized hard coat layer comprises a UV cured acrylate or a thermally cured planarizier.

14. The method according to claim 9 , wherein the methylsiloxane in step d) has a methyl content in the range of from ≧6 wt.-% to ≦11.5 wt.-%.

Assignees

• Covestro Deutschland Ag

Inventors

• Ou Eric Chuan Whatt
• Sankaran Sivaramakrishan
• Ma Khine Myat Sint
• Häβler Christian
• Schmidt Axel

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H01L21/0274

  Electricity · mapped topic