Semiconductor device and related fabrication methods

Patent metadata

Field	Value
Publication number	US-9070576-B2
Application number	US-201213606797-A
Country	US
Kind code	B2
Filing date	Sep 7, 2012
Priority date	Sep 7, 2012
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type, the doped region overlying an insulating layer of dielectric material, the method comprising:
forming a first region having a second conductivity type within the doped region by implanting ions of the second conductivity type at a first energy level using an implantation mask;
forming a body region having the first conductivity type overlying the first region by implanting ions of the first conductivity type at a second energy level using the implantation mask, the second energy level being less than the first energy level; and
forming a drift region having the second conductivity type within the doped region by implanting ions of the second conductivity type using a second implantation mask, the second implantation mask masking the body region and having lateral edges offset from lateral boundaries of the body region, wherein:
at least a portion of the drift region abuts at least a portion of the first region;
a first thickness of a first portion of the doped region between the first region and the insulating layer is less than a second thickness of a second portion of the doped region between the drift region and the insulating layer; and
a portion of the doped region remains between the body region and the drift region.

2. The method of claim 1 , wherein:
forming the first region comprises implanting ions of the second conductivity type having a first dopant concentration using the implantation mask;
forming the body region comprises implanting ions of the first conductivity type having a second dopant concentration using the implantation mask; and
the second dopant concentration is greater than the first dopant concentration.

3. The method of claim 2 , wherein:
forming the drift region comprises implanting ions of the second conductivity type having a third dopant concentration using the second implantation mask; and
the third dopant concentration different from the first dopant concentration.

4. The method of claim 2 , wherein:
forming the first region comprises implanting ions of the second conductivity type having the first dopant concentration at a first energy level;
forming the body region comprises implanting ions of the first conductivity type having the second dopant concentration at a second energy level; and
the second energy level is less than the first energy level.

5. The method of claim 4 , wherein:
forming the drift region comprises implanting ions of the second conductivity type having a third dopant concentration at a third energy level using a second implantation mask; and
the third energy level is less than the first energy level.

6. The method of claim 1 , wherein:
implanting ions of the second conductivity type at the first energy level comprises implanting the ions of the second conductivity type at an energy level greater than or equal to 1 megaelectron volt; and
implanting ions of the first conductivity type at the second energy level comprises implanting the ions of the first conductivity type at an energy level less than or equal to 300 kiloelectron volts.

7. The method of claim 1 , wherein:
forming the drift region comprises implanting ions of the second conductivity type at a third energy level using the second implantation mask; and
the third energy level is greater than the second energy level.

8. A method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type, the method comprising:
forming a first region having a second conductivity type within the doped region by implanting ions of the second conductivity type at a first energy level using an implantation mask;
forming a body region having the first conductivity type overlying the first region by implanting ions of the first conductivity type at a second energy level using the implantation mask, wherein the second energy level is less than the first energy level; and
forming a drift region having the second conductivity type within the doped region, by implanting ions of the second conductivity type using a second implantation mask, the second implantation mask masking the body region and having lateral edges offset from lateral boundaries of the body region, wherein:
a portion of the doped region remains between the body region and the drift region; and
at least a portion of the drift region abuts at least a portion of the first region.

9. The method of claim 1 , further comprising:
forming an isolation region of dielectric material within the doped region;
forming a drain contact region within the drift region, the drain contact region having the second conductivity type, wherein the isolation region is between the drain contact region and the body region;
forming a gate structure overlying at least a portion of the body region, a portion of the drift region between the isolation region and the portion of the body region, and at least a portion of the isolation region; and
forming a source contact region within the body region proximate the gate structure.

10. The method of claim 9 , further comprising epitaxially growing at least a portion of the doped region on a semiconductor substrate, the semiconductor substrate comprising the insulating layer overlying a handle layer of semiconductor material.

11. A semiconductor device structure comprising:
a drift region of semiconductor material having a first conductivity type;
a drain region of semiconductor material within the drift region, the drain region having the first conductivity type;
a body region of semiconductor material having a second conductivity type;
a buried region of semiconductor material having the first conductivity type;
a doped region of semiconductor material having the second conductivity type; and
an insulating layer of dielectric material, wherein:
a first portion of the doped region overlies the insulating layer between the buried region and the insulating layer;
a second portion of the doped region overlies the insulating layer between the drift region and the insulating layer;
the body region overlies a first portion the buried region;
a lower portion of the drift region abuts at least a second portion of the buried region; and
the drift region is formed using an implantation mask masking the body region and having lateral edges offset from lateral boundaries of the body region such that a third portion of the doped region remains between the body region and the drift region.

12. The semiconductor device structure of claim 11 , wherein a dopant concentration of the buried region is different from a dopant concentration of the drift region.

13. The semiconductor device structure of claim 12 , wherein a dopant concentration of the body region is greater than the dopant concentration of the buried region.

14. The semiconductor device structure of claim 11 , wherein a lower boundary of the buried region extends below a lower boundary of the drift region.

15. The semiconductor device structure of claim 11 , further comprising:
an isolation region of dielectric material between the drain region and the body region.

16. The semiconductor device structure of claim 11 , wherein a distance between a lower boundary of the drift region and the insulating layer is greater than a distance between a lower boundary of the buried region and the insulating layer.

17. The semiconductor device structure of claim 11 , wherein a thickness of the first portion of the

Assignees

• Yang Hongning
• Zhang Zhihong
• Zuo Jiang-Kai
• Freescale Semiconductor Inc

Inventors

• Yang Hongning
• Zhang Zhihong
• Zuo Jiang-Kai

Classifications

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title