Chip packages and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9735130-B2
Application number	US-201414472699-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A chip package may include: a first die; at least one second die disposed over the first die; and a lid disposed over lateral portions of the first die and at least partially surrounding the at least one second die, the lid having inclined sidewalls spaced apart from and facing the at least one second die.

First claim

What is claimed is:

1. A chip package comprising:
a first integrated circuit die;
at least one second integrated circuit die disposed over the first integrated circuit die; and
a lid disposed over lateral portions of the first integrated circuit die and at least partially surrounding the at least one second integrated circuit die, the lid having inclined sidewalls spaced apart from and facing the at least one second integrated circuit die, the lid continuously extending laterally from the inclined sidewalls to a vertical outer edge of the lid, wherein
no portion of the lid is disposed over the at least one second integrated circuit die,
a top surface of an uppermost die of the at least one second integrated circuit die has a first distance to a top surface of the first integrated circuit die,
a topmost surface of the lid has a second distance to the top surface of the first integrated circuit die,
the first distance being larger than the second distance, and
the first distance and the second distance are measured in a direction orthogonal to a plane formed by the top surface of the uppermost die of the at least one second integrated circuit die.

2. The chip package of claim 1 , wherein a portion of the inclined sidewalls proximate the first integrated circuit die is spaced apart from the at least one second integrated circuit die by a first distance, wherein a portion of the inclined sidewalls distal the first integrated circuit die is spaced apart from the at least one second integrated circuit die by a second distance greater than the first distance.

3. The chip package of claim 2 , wherein the first distance is in a range from about 100 micrometers to about 300 micrometers.

4. The chip package of claim 2 , wherein the second distance is in a range from about 300 micrometers to about 700 micrometers.

5. The chip package of claim 1 , wherein an incline angle of the inclined sidewalls of the lid is in a range from about 45 degrees to about 75 degrees.

6. The chip package of claim 1 , wherein a lateral extent of the lateral portions of the first integrated circuit die over which the lid is disposed is in a range from about 600 micrometers to about 1000 micrometers.

7. The chip package of claim 1 , further comprising a molding compound disposed between the inclined sidewalls of the lid, the molding compound at least partially encapsulating the at least one second integrated circuit die.

8. The chip package of claim 1 , further comprising a heat sink disposed over the at least one second integrated circuit die, wherein a lateral extent of the heat sink is larger than a lateral extent of the first integrated circuit die.

9. The chip package of claim 1 , further comprising a substrate, wherein the first integrated circuit die is disposed over the substrate.

10. A chip package comprising:
a semiconductor substrate;
a first die disposed over the semiconductor substrate;
at least one second die disposed over the first die;
a lid at least partially surrounding the first die and the at least one second die, the lid having first portions and overhanging portions, the first portions of the lid disposed over the semiconductor substrate and spaced apart from the first die, the overhanging portions of the lid disposed over the first portions of the lid and extending towards the at least one second die, the overhanging portions of the lid and the first portions of the lid comprising a continuous and homogenous material, the overhanging portions of the lid disposed over lateral portions of the first die and spaced apart from the at least one second die, wherein no portion of the lid is disposed over the at least one second die; and
a molding compound at least partially encapsulating the at least one second die and disposed over a surface of the first die between the lateral portions of the first die, wherein a top surface of a topmost die of the at least one second die is offset in a direction perpendicular to the top surface of the topmost die of the at least one second die with a top surface of the molding compound and a top surface of the lid,
wherein the top surface of the topmost die of the at least one second die is a first distance from the surface of the first die in the perpendicular direction,
wherein the top surface of the molding compound and the top surface of the lid are a second distance from the surface of the first die in the perpendicular direction, and
wherein the offset causes the first distance to be greater than the second distance.

11. The chip package of claim 10 , wherein the overhanging portions of the lid have inclined sidewalls disposed over the lateral portions of the first die and facing the at least one second die.

12. The chip package of claim 11 , wherein an incline angle of the inclined sidewalls of the overhanging portions of the lid is in a range from about 45 degrees to about 75 degrees.

13. The chip package of claim 10 , further comprising:
a first adhesive layer disposed between the first portions of the lid and the semiconductor substrate; and
a second adhesive layer disposed between the overhanging portions of the lid and the lateral portions of the first die.

14. The chip package of claim 10 , wherein a surface of the molding compound facing away from the first die is substantially co-planar with a surface of the lid facing away from the semiconductor substrate.

15. The chip package of claim 10 , wherein the molding compound is in direct physical contact with surfaces of the overhanging portions of the lid facing the at least one second die.

16. The chip package of claim 10 , further comprising a heat sink disposed over the overhanging portions of the lid and the at least one second die, wherein a third adhesive layer is disposed between the heat sink and the lid, wherein a fourth adhesive layer is disposed between the at least one second die and the heat sink, and wherein an air gap is disposed laterally between the third adhesive layer and the fourth adhesive layer.

17. A chip package, comprising:
a first die disposed over a substrate;
at least one second die stacked over the first die;
a conductive lid having first portions disposed over the substrate and laterally separated from the first die, the conductive lid further having overhanging portions disposed over the first portions of the conductive lid and lateral portions of the first die, the overhanging portions of the conductive lid laterally separated from the at least one second die; and
a molding compound encapsulating a top, bottom, and side walls of the at least one second die, wherein no portion of the conductive lid covers the at least one second die, wherein
no portion of the conductive lid is disposed over the at least one second die,
a topmost surface of a topmost die of the at least one second die is in a first plane,
a topmost surface of the molding compound is in a second plane, and
the first plane and the second plane are offset,
wherein a top surface of the substrate is in a third plane, the first plane being at a first distance from the third plane, the second plane being at a second distance from the third plane, and the first distance being larger than the second distance, the first and second distances measured orthogonally to the first plane.

18. The chip package of claim 17 , further comprising a heat sink attached to surfaces of the conductive lid facing away from the substrate.

19. The chip package of claim 17 , further comprising a first adhesive layer attaching the first portions of the conductive lid t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Kuo Lung
• Huang Ying-Jui
• Chen Yu-Feng
• Chen Chen-Shien

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W76/18

  Insulating materials, e.g. resins, glasses or ceramics · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W76/67

  characterised by their materials · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title