Low z-height package assembly

Patent metadata

Field	Value
Publication number	US-9735120-B2
Application number	US-201314138754-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die and one or more of the conductive pads. The package assembly may further include a solder resist layer coupled with the die and the conductive pads, and one or more interconnects positioned at least partially within the solder resist layer and directly coupled with one or more of the conductive pads.

First claim

What is claimed is:

1. A package assembly comprising:
a die having a first side and a second side opposite the first side, wherein the die includes one or more traces on the first side;
one or more pads, wherein a first pad of the one or more pads has a first side and a second side opposite the first side, the first side of the first pad is coupled with the first side of the die and one of the one or more traces;
a metal outer layer directly coupled to, and positioned over, the second side of the first pad, wherein the outer layer partially covers an edge part of the second side of the first pad, and a middle part of the second side of the first pad is not covered by the outer layer;
a solder ball directly coupled with the second side of the first pad; and
a barrier layer directly coupled with the first side of the first pad and disposed between the first side of the first pad and the first side of the die.

2. The package assembly of claim 1 , wherein the barrier layer includes a first side and a second side, and wherein the first side of the barrier layer is directly coupled with the first side of the first pad, and wherein the second side of the barrier layer is directly coupled with the first side of the die.

3. The package assembly of claim 1 , wherein the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or titanium tungstate.

4. The package assembly of claim 1 , wherein the first pad and a second pad of the one or more pads define a cavity between the first pad and the second pad, the cavity being disposed directly adjacent to the first side of the die.

5. The package assembly of claim 1 , wherein the first side of the first pad has a surface that is not chemically roughened.

6. The package assembly of claim 4 , further comprising a solder resist layer directly coupled to the first side of the die in the cavity and at least part of the second side of the first pad.

7. The package assembly of claim 1 , wherein the second side of the first pad has a roughened surface completely covering the second side of the first pad.

8. The package assembly of claim 1 , wherein the one or more pads include copper.

9. The package assembly of claim 1 , further comprising a dielectric layer coupled with at least the second side of the die, and surrounding the die such that the dielectric layer is level with the first side of the die, and wherein the barrier layer is directly coupled with the dielectric layer.

10. A method comprising:
depositing a barrier layer directly on a first side of a die;
forming a first pad and a second pad directly on the barrier layer;
chemically roughening the first pad and the second pad; and
removing a portion of the barrier layer such that a portion of the barrier layer remains disposed between the first pad and the first side of the die and between the second pad and the first side of the die; and
forming a metal outer layer directly coupled to, and positioned over, the first pad on a side of the first pad opposite the barrier layer, wherein the outer layer partially covers an edge part of the side of the first pad, and a middle part of the side of the first pad is not covered by the outer layer; and
directly coupling a solder ball with the side of the first pad.

11. The method of claim 10 , wherein the barrier layer is sputter deposited.

12. The method of claim 10 , wherein the barrier layer includes titanium.

13. The method of claim 10 , wherein the first pad includes copper.

14. The method of claim 10 , wherein the chemically roughening includes chemically etching the first pad and the second pad with a peroxide based solution.

15. The method of claim 10 , further comprising depositing, after the depositing the barrier layer, a seed material on the barrier layer prior to depositing the first pad and the second pad.

16. The method of claim 10 , further comprising:
depositing a solder resist layer directly on the first side of the die and the chemically roughened first pad and second pad;
forming a cavity in the solder resist layer such that the chemically roughened first pad is exposed; and
attaching a conductive element directly to the chemically roughened first pad in the cavity.

17. A system with a package assembly, the system comprising:
a circuit board; and
a package assembly coupled with the circuit board, the package assembly comprising:
a die having a first side and a second side opposite the first side, wherein the die includes one or more traces on the first side;
one or more pads, wherein a first pad of the one or more pads has a first side and a second side opposite the first side, and wherein the first side of the first pad is coupled with the first side of the die;
a metal outer layer directly coupled to, and positioned over the second side of the first pad, wherein the outer layer partially covers an edge part of the second side of the first pad, and a middle part of the second side of the first pad is not covered by the outer layer;
a solder ball directly coupled with the second side of the first pad; and
a barrier layer directly coupled with the first side of the first pad and disposed between the first side of the first pad and the first side of the die.

18. The system of claim 17 , wherein the first pad and a second pad of the one or more pads define a cavity between the first pad and the second pad, the cavity being disposed directly over the first side of the die.

19. The system of claim 18 , wherein the second side of the first pad has a roughened surface and the first side of the first pad has a surface that is not roughened.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Boyapati Sri Ranga Sai

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title