Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP

Patent metadata

Field	Value
Publication number	US-9735113-B2
Application number	US-78600810-A
Country	US
Kind code	B2
Filing date	May 24, 2010
Priority date	May 24, 2010
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a temporary carrier;
providing a plurality of first semiconductor die each including an active surface and back surface opposite the active surface;
mounting the back surfaces of the plurality of first semiconductor die to the temporary carrier;
mounting a plurality of second semiconductor die over the plurality of first semiconductor die with an active surface of each of the plurality of second semiconductor die oriented toward the respective active surfaces of the plurality of first semiconductor die;
forming a plurality of bumps over the active surfaces of the plurality of first semiconductor die around a respective perimeter of each of the plurality of second semiconductor die;
depositing an encapsulant over the plurality of first semiconductor die, the plurality of second semiconductor die, and the temporary carrier;
forming a plurality of conductive vias partially through the encapsulant around the plurality of first semiconductor die and the plurality of second semiconductor die;
removing a first portion of the encapsulant and the plurality of first semiconductor die to expose the conductive vias;
forming a first interconnect structure over the encapsulant and the back surfaces of the plurality of first semiconductor die, the interconnect structure being electrically connected to the conductive vias; and
removing the temporary carrier.

2. The method of claim 1 , further including removing a second portion of the encapsulant and a portion of a back surface of each of the plurality of second semiconductor die opposite the active surfaces.

3. The method of claim 1 , further including forming a conductive layer over the encapsulant and the back surfaces of the plurality of first semiconductor die, the conductive layer being electrically connected to the conductive vias.

4. The method of claim 1 , further including mounting a heat sink over the encapsulant and the back surfaces of the plurality of first semiconductor die or a back surface of the plurality of second semiconductor die.

5. The method of claim 1 , further including forming a shielding layer over the encapsulant and the back surfaces of the plurality of first semiconductor die or a back surface of the plurality of second semiconductor die.

6. The method of claim 1 , further including:
providing an electrical component; and
mounting the electrical component to the semiconductor device, the electrical component being electrically connected to the conductive vias.

Assignees

• Chi Heejo
• Cho Namju
• Myung Junwoo
• Stats Chippac Pte Ltd

Inventors

• Chi Heejo
• Cho Namju
• Myung Junwoo

Classifications

• H05K3/426

  initial plating of through-holes in substrates without metal · CPC title

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K3/0052

  Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards · CPC title

• H05K3/007

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title