Systems and methods for thermal control of integrated circuits

Patent metadata

Field	Value
Publication number	US-9735088-B2
Application number	US-201514963181-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side opposite the first side. The second side of the IC die is coupled to the carrier. The system includes a die attach layer between the carrier and the second side of the IC die. The die attach layer defines one or more openings that enable a fluid to flow from the carrier to the second side of the IC die.

First claim

What is claimed is:

1. A device comprising:
a carrier defining a plurality of channels; and
an integrated circuit (IC) die having a first side and having a second side opposite the first side, the second side of the IC die coupled to the carrier, the IC die including part of an electrically conductive path between the first side of the IC die and the carrier, the plurality of channels configured to route a fluid to a first portion of the second side of the IC die, wherein the electrically conductive path includes a second portion of the second side of the IC die, and wherein the first portion of the second side of the IC die is distinct from the second portion of the second side of the IC die.

2. The device of claim 1 , wherein the first portion of the second side of the IC die corresponds to an etch indent in the IC die, and wherein at least one of the plurality of channels is configured to route the fluid through the etch indent.

3. The device of claim 1 , wherein the IC die includes a field effect transistor, wherein the first side of the IC die includes an active region of the field effect transistor, wherein the active region at least partially overlaps the second portion of the second side of the IC die, and wherein the second portion of the second side of the IC die does not overlap the active region.

4. The device of claim 1 , wherein the IC die includes part of a second conductive path between the first side of the IC die and the carrier, wherein at least one of the plurality of channels is configured to route the fluid to a third portion of the second side of the IC die, wherein the electrically conductive path includes a fourth portion of the second side of the IC die, wherein the first portion of the second side of the IC die is distinct from the fourth portion of the second side of the IC die, wherein the third portion of the second side of the IC die is distinct from the second portion of the second side of the IC die or the fourth portion of the second side of the IC die.

5. The device of claim 4 , wherein wherein the second portion of the IC die is located between the first portion of the second side of the IC die and the third portion of the IC die, and wherein the third portion of the IC die is located between the second portion of the second side of the IC die and the fourth portion of the IC die.

6. The device of claim 1 , wherein the carrier includes a base and a platform, wherein the base is coupled to the platform and defines a plurality of ports, wherein the platform includes at least three layers to define the plurality of channels, wherein the at least three layers include a first layer having a first void area, a second layer having a second void area, and a third layer having a third void area, wherein the plurality of channels is defined by the first void area, the second void area, and the third void area.

7. The device of claim 6 , wherein the first void area is smaller than the second void area and the second void area is smaller than the third void area, wherein the third void area is defined by at least two separate void portions, wherein the second void area is defined by at least six separate void portions and the first void area is defined by at least six separate void portions, and wherein the first layer is between the third layer and the IC die and the second layer is between the first layer and the third layer.

8. The device of claim 6 , wherein the second void area overlaps a portion of the third void area, and wherein the first void area overlaps a portion of the second void area.

9. A device comprising:
a carrier defining a plurality of channels;
an integrated circuit (IC) die having a first side and having a second side opposite the first side, the second side of the IC die coupled to the carrier, the IC die including part of an electrically conductive path between the first side of the IC die and the carrier; and
a seal between the carrier and the second side of the IC die, wherein the seal attaches the carrier to the second side of the IC die, and wherein the seal has a plurality of openings that enable a fluid to flow from the carrier to a first portion of the second side of the IC die, wherein the electrically conductive path includes a second portion of the second side of the IC die, and wherein the first portion of the second side of the IC die is distinct from the second portion of the second side of the IC die.

10. The device of claim 9 , wherein the seal is formed of gold, tin, conductive epoxy, or a combination thereof.

11. The device of claim 9 , wherein at least one of the plurality of openings overlaps at least a portion of the plurality of channels.

12. The device of claim 9 , wherein the carrier, the plurality of openings, and the second side of the IC die define a cavity to receive the fluid.

13. The device of claim 9 , wherein the seal forms a hermetic seal between the carrier and the second side of the IC die.

14. The device of claim 9 , wherein the second side of the IC die includes multiple etch indents, and wherein at least a portion of each etch indent of the multiple etch indents is proximate to at least a portion of a corresponding opening of the plurality of openings.

15. The device of claim 9 , wherein the seal provides part of the electrically conductive path between the carrier and the first side of the IC die.

16. A method of assembling, comprising:
aligning a carrier with an integrated circuit (IC) die to expose an etch indent at a substrate of the IC die to a plurality of channels defined by the carrier, the IC die having a first side and having a second side opposite the first side, the etch indent corresponding to a first portion of the second side of the IC die; and
forming a hermetic seal between the carrier and the IC die by performing a die attach process to attach the carrier and the IC die using a die attach layer positioned between the IC die and the carrier, the hermetic seal coupling the second side to the carrier, wherein the die attach layer defines one or more openings that enable a fluid to flow from the carrier to the etch indent, wherein the die attach process includes subjecting the carrier, the die attach layer, and the IC die to controlled heat to cause reflow of the die attach layer, wherein the IC die includes part of an electrically conductive path between the first side of the IC die and the carrier, wherein the electrically conductive path includes a second portion of the second side of the IC die, and wherein the first portion of the second side of the IC die is distinct from the second portion of the second side of the IC die.

17. The method of claim 16 , further comprising electrically coupling the second side of the IC die to the carrier via the electrically conductive path.

18. The method of claim 16 , wherein each opening of the one or more openings defined by the die attach layer is aligned with the etch indent such that each opening of the one or more openings is proximate to the etch indent.

19. The device of claim 6 , wherein each port of the plurality of ports includes a first portion at a first side of the base and a second portion at a second side of the base, wherein the second side is opposite the first side, and wherein the first portion of each port of the plurality of ports has different dimensions than the second portion of each port of the plurality of ports.

20. The device of claim 19 , wherein a first void portion of the third void area overlaps a first port of the plurality of ports, wherein a second void p

Assignees

• Woolrich Kyle A
• Allison Jonathan M
• Rust Iii Thomas
• Silhavy Robert E
• Boeing Co

Inventors

• Woolrich Kyle A
• Allison Jonathan M
• Rust Iii Thomas
• Silhavy Robert E

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W40/47 Primary

  by flowing liquids, e.g. forced water cooling · CPC title

• H10W40/40 Primary

  involving heat exchange by flowing fluids · CPC title

• H01L27/0296

  Electricity · mapped topic

• H01L23/46 Primary

  Electricity · mapped topic