Single-layer wiring package substrate, single-layer wiring package structure having the package substrate, and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9735080-B2
Application number	US-201514876404-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Dec 4, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

First claim

What is claimed is:

1. A single-layer wiring package substrate, comprising:
a wiring layer having opposing first and the second surfaces; and
a dielectric body having a first side with a first opening and a second side opposing the first side, wherein a portion of the wiring layer is exposed from the first opening, and the second side of the dielectric body and the second surface of the wiring layer are disposed at a same side, and wherein a second opening is formed on the first surface of the wiring layer and communicated with the first opening.

2. The single-layer wiring package substrate of claim 1 , wherein the dielectric body is made of a photosensitive dielectric material.

3. The single-layer wiring package substrate of claim 1 , wherein the second side of the dielectric body is coplanar with the second surface of the wiring layer.

4. A package structure, comprising:
the single-layer wiring package substrate of claim 1 ; and
a semiconductor component disposed on the second side of the dielectric body and electrically connected with the second surface of the wiring layer.

5. The package structure of claim 4 , wherein the semiconductor component has a plurality of conductive bumps electrically connected with the second surface of the wiring layer.

6. The package structure of claim 5 , further comprising an underfill filled between the semiconductor component and the second side of the dielectric body.

7. The package structure of claim 4 , further comprising an encapsulant formed on the dielectric body and encapsulating the semiconductor component.

8. The package structure of claim 4 , wherein the dielectric body is made of a photosensitive dielectric material.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chiu Shih-Chao
• Lin Chun-Hsien
• Pai Yu-Cheng
• Hsiao Wei-Chung
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title