Electronic module and fabrication method thereof

US9735075B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9735075-B2
Application numberUS-201414516010-A
CountryUS
Kind codeB2
Filing dateOct 16, 2014
Priority dateSep 3, 2014
Publication dateAug 15, 2017
Grant dateAug 15, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic module, comprising: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface connecting the active and inactive surfaces; a passivation layer formed on the active surface with the electrode pads exposed from the passivation layer; a strengthening layer formed on the side surface of the electronic element and being free from being formed on the passivation layer on the active surface of the electronic element; and an RDL structure formed on and in direct contact with the strengthening layer and the passivation layer on the active surface of the electronic element and electrically connected to the electrode pads of the electronic element. 2. The module of claim 1 , wherein the electronic element is bonded to a packaging substrate via the active surface thereof. 3. The module of claim 1 , wherein the strengthening layer is further formed on the inactive surface of the electronic element. 4. The module of claim 1 , wherein the strengthening layer is formed around the side surface of the electronic element. 5. The module of claim 1 , wherein the strengthening layer is made of an insulating material. 6. The module of claim 1 , further comprising a separation portion formed on the strengthening layer on the side surface of the electronic element in a manner that the strengthening layer is sandwiched between the side surface of the electronic element and the separation portion. 7. The module of claim 6 , wherein the separation portion has a width less than 1 mm. 8. The module of claim 6 , wherein the RDL structure is further formed on the separation portion. 9. The module of claim 1 , further comprising a plurality of conductive elements formed on the RDL structure and electrically connected to the electrode pads of the electronic element.

Assignees

Inventors

Classifications

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

  • using batch processing · CPC title

  • on encapsulations · CPC title

  • Dispositions, e.g. layouts · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9735075B2 cover?
An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.
Who is the assignee on this patent?
Siliconware Precision Industries Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W76/40. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 15 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).