Method of forming a temporary test structure for device fabrication

Patent metadata

Field	Value
Publication number	US-9735071-B2
Application number	US-201514835449-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Aug 25, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects and for electrical testing. The suitable material for the temporary test structure is TiW for a single layer structure, or Cu or Cu alloy over Ti or TiW for a bilayer structure with thickness in a range of about 20 nm to 1200 nm. Excimer laser ablation can be used to form the temporary test structure. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance, and the substrate can be further processed with normal processes. The temporary test structure may contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

First claim

What is claimed is:

1. A method of forming a temporary test structure for device fabrication comprising:
providing a substrate comprising a plurality of electrically conductive interconnects extending vertically to top surface of the substrate;
conformally forming an electrical test layer on top of the substrate, the electrical test layer connecting to the plurality of electrically conductive interconnects;
patterning the electrical test layer by selectively removing portions of the electrical test layer to form a temporary test structure which comprises unremoved portions of the electrical test layer and comprises providing electrical connection between at least a first test location and a second test location, wherein the first and second test locations are each electrically connected to at least one of the plurality of electrically conductive interconnects;
performing electrical testing by probing at least the first test location and the second test location on the temporary test structure; and
removing all or part of the temporary test structure.

2. The method of claim 1 , wherein removing part of the temporary test structure comprises removing more than 50% of the temporary test structure.

3. The method of claim 1 , wherein material of the electrical test layer is selected from a group consisting of copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), ruthenium (Ru), chromium (Cr), iridium (Ir), osmium (Os), palladium (Pd), platinum (Pt), and alloys and ceramics thereof.

4. The method of claim 3 , wherein material of the electrical test layer comprises titanium tungsten alloy (Ti—W) in a single layer, or comprises copper (Cu) or Cu alloy over titanium (Ti) or titanium tungsten alloy (Ti—W) in a bilayer.

5. The method of claim 1 , wherein thickness of the electrical test layer is in a range of about 20 nm to 1200 nm.

6. The method of claim 1 , wherein patterning the electrical test layer by selectively removing portions of the electrical test layer to form a temporary test structure comprises:
performing a laser ablation on the electrical test layer using an excimer laser through an ablation mask, which comprises an electrical testing pattern, to selectively remove portions of the electrical test layer; and
removing loose material of the electrical test layer to form the temporary test structure comprising the electrical testing pattern.

7. The method of claim 1 , wherein the temporary test structure comprises electrical test pads.

8. The method of claim 7 , wherein the electrical test pads are in kerf area.

9. The method of claim 1 , wherein after conformally forming an electrical test layer and before patterning the electrical test layer the method further comprises:
forming C4 bumps over the plurality of electrically conductive interconnects.

10. The method of claim 1 , wherein removing all or part of the temporary test structure comprises wet chemical etching, reactive ion etching, inert gas sputtering, or laser ablation.

11. The method of claim 1 , wherein performing electrical testing comprises probing the temporary test structure with a cobra probe.

Assignees

• IBM

Inventors

• Arvin Charles L
• Erwin Brian Michael
• Maier Gary W

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title