Fabricating method of semiconductor structure

Patent metadata

Field	Value
Publication number	US-9735015-B1
Application number	US-201615369878-A
Country	US
Kind code	B1
Filing date	Dec 5, 2016
Priority date	Dec 5, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of manufacturing a semiconductor structure, comprising: providing a preliminary structure having a first region and a second region and comprising a plurality of first trenches in the first region; forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening; forming a metal nitride layer on the metal layer by an nitride treatment; and performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing a preliminary structure having a first region and a second region, and the preliminary structure comprising a plurality of first trenches in the first region;
forming a metal layer filling the first trenches covering on the preliminary structure, wherein the metal layer comprises a concave portion in the second region and the concave portion defines an opening;
forming a metal nitride layer on the metal layer by a nitride treatment; and
performing a planarization process to remove the metal nitride layer and a portion of the metal layer to expose the preliminary structure.

2. The method of manufacturing the semiconductor structure according to claim 1 , wherein the preliminary structure further comprises a second trench in the second region, and a second width of the second trench is larger than a first width of the first trench.

3. The method of manufacturing the semiconductor structure according to claim 2 , wherein the first width is in a range of 30-80 angstroms and the second width is in a range of 50-500 nm.

4. The method of manufacturing the semiconductor structure according to claim 2 , wherein the opening of the concave portion is in an area covered by the second trench.

5. The method of manufacturing the semiconductor structure according to claim 2 , wherein the semiconductor structure is a fin-shaped field effect transistor and the step of providing the preliminary structure comprises:
providing a substrate;
forming a fin structure by removing a portion of the substrate;
forming a dummy gate layer comprising a plurality of dummy gate bars, the dummy gate bars have different widths and are disposed parallelly across on the fin structure;
forming a plurality of different pairs of spacers on two opposite sidewalls of each of the dummy gate bars;
removing a portion of the fin structure by using the dummy gate layers and the different pairs of spacers as a mask;
epitaxially growing a source/drain structure on two sides of each of the dummy gate bars, where the portion of the fin structure is removed;
forming an interlayer dielectric layer on the source/drain structure in-between the different pairs of the spacers; and
removing the dummy gate layer to form the first trenches in the first regions and the second trench in the second region.

6. The method of manufacturing the semiconductor structure according to claim 1 , wherein the metal layer is a tungsten layer.

7. The method of manufacturing the semiconductor structure according to claim 6 , wherein the tungsten layer is formed by a seam suppressed tungsten gap fill process.

8. The method of manufacturing the semiconductor structure according to claim 1 , wherein the nitride treatment uses nitrogen gas having a flow rate in a range of 1-10 sccm.

9. The method of manufacturing the semiconductor structure according to claim 1 , wherein a duration time of the nitride treatment is in a range of 3-30 seconds.

10. The method of manufacturing the semiconductor structure according to claim 9 , wherein the duration time of the nitride treatment is in a range of 3-8 seconds.

11. The method of manufacturing the semiconductor structure according to claim 1 , wherein a power of the nitride treatment is in a range of 500-2500 watt.

12. The method of manufacturing the semiconductor structure according to claim 1 , wherein the metal layer has a total thickness in a range of 1600-2200 angstroms.

13. The method of manufacturing the semiconductor structure according to claim 1 , wherein the metal layer has an overall average thickness of 2000 angstroms.

14. The method of manufacturing the semiconductor structure according to claim 1 , wherein the metal layer has a thickness above the preliminary structure in a range of 500-800 angstroms.

15. The method of manufacturing the semiconductor structure according to claim 14 , wherein the metal layer has a thickness above the preliminary structure in a range of 700-800 angstroms.

16. The method of manufacturing the semiconductor structure according to claim 1 , wherein the first trench has a depth in a range of 300-500 angstroms.

17. The method of manufacturing the semiconductor structure according to claim 1 , wherein the step of forming the metal nitride layer comprises:
forming a metal nucleation layer covering the metal layer;
introducing nitride radicals onto the metal nucleation layer to transform the metal nucleation layer into a metal nitride seed layer; and
performing a chemical vapor deposition process to form the metal nitride layer.

18. The method of manufacturing the semiconductor structure according to claim 17 , wherein the metal nucleation layer has the same metal material as the metal layer.

19. The method of manufacturing the semiconductor structure according to claim 17 , wherein the metal nucleation layer is a tungsten nucleation layer and the metal nitride seed layer is a tungsten nitride seed layer.

Assignees

• United Microelectronics Corp

Inventors

• Li Kun Ju
• Liu Hsin Jung
• Tsai Wei-Chuan
• Tsai Min-Chuan
• Liao Yi Han
• Lu Chun-Tsen
• Chen Chun-Lin
• Yang Jui-Ming
• Hung Kuo-Chin

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H01L29/66795

  Electricity · mapped topic