Area-delay-power efficient multibit flip-flop

Patent metadata

Field	Value
Publication number	US-9729128-B2
Application number	US-201514682413-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Apr 9, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.

First claim

We claim:

1. A multi-bit flip-flop comprising:
a plurality of flip-flops, each having a corresponding input data selection circuit coupled to receive a corresponding input data signal and a corresponding scan input data signal; and
a local signal generation circuit coupled to receive a global clock signal and a global scan enable signal, and in response, provide a plurality of local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal, wherein the local control signals are provided to each of the input data selection circuits, and wherein the local control signals exclusively control the input data selection circuits.

2. The multi-bit flip-flop of claim 1 , wherein each of the input data selection circuits includes exactly eight transistors.

3. The multi-bit flip-flop of claim 1 , wherein each of the plurality of flip-flops further includes a corresponding master latch circuit coupled to receive the corresponding input data signal or the corresponding scan input data signal from the corresponding input data selection circuit based on the local control signals.

4. The multi-bit flip-flop of claim 3 , wherein each of the plurality of flip-flops further includes:
a corresponding slave latch circuit; and
a corresponding transfer circuit that couples the corresponding master latch circuit to the corresponding slave latch circuit.

5. The multi-bit flip-flop of claim 4 , wherein the local signal generation circuit further includes a local clock generation circuit for generating local clock signals in response to the global clock signal, wherein the transfer circuit within each of the plurality of flip-flops is controlled exclusively by the local clock signals.

6. The multi-bit flip-flop of claim 5 , wherein the local signal generation circuit is further coupled to receive a global reset signal, and provide a local reset control signal in response to both the global reset signal and the global clock signal, wherein the local reset control signal is applied to each of the plurality of flip-flops.

7. The multi-bit flip-flop of claim 1 , wherein the local signal generation circuit includes a local clock generation circuit for generating local clock signals in response to the global clock signal, wherein the local clock signals exclusively control data transfer between a master latch circuit and a slave latch circuit within each of the plurality of flip-flops.

8. The multi-bit flip-flop of claim 1 , wherein the local signal generation circuit includes:
an inverter that provides a first local clock signal in response to the global clock signal;
a first inverter that provides a local scan enable signal in response to the global scan enable signal;
a first NAND gate that provides a first local control signal in response to the first local clock signal and the local scan enable signal; and
a second NAND gate that provides a second local control signal in response to the first local clock signal and the global scan enable signal.

9. The multi-bit flip-flop of claim 8 , further comprising:
a second inverter that provides a third local control signal in response to the first local control signal; and
a third inverter that provides a fourth local control signal in response to the second local control signal.

10. The multi-bit flip-flop of claim 1 , wherein the input data selection circuit within each of the plurality of flip-flops comprises:
a first transistor and a second transistor coupled in series between a first voltage supply terminal and a first node, wherein the first transistor is controlled by a first one of the local control signals, and the second transistor is controlled by the input data signal;
a third transistor and a fourth transistor coupled in series between the first node and a second voltage supply terminal, wherein the third transistor is controlled by the input data signal, and the fourth transistor is controlled by a second one of the local control signals;
a fifth transistor and a sixth transistor coupled in series between the first voltage supply terminal and the first node, wherein the fifth transistor is controlled by a third one of the local control signals, and the sixth transistor is controlled by the scan input data signal; and
a seventh transistor and an eighth transistor coupled in series between the first node and the second voltage supply terminal, wherein the seventh transistor is controlled by the scan input data signal, and the eighth transistor is controlled by a fourth one of the local control signals.

11. The multi-bit flip-flop of claim 10 , wherein the first, second, third, fourth, fifth, sixth, seventh and eighth transistors are the only transistors of the input data selection circuit.

12. The multi-bit flip-flop of claim 1 , wherein the local signal generation circuit includes:
an inverter chain that provides a first local clock signal and a second local clock signal in response to the global clock signal,
and wherein each of the plurality of flip-flops includes:
a transfer circuit comprising a first transistor coupled in parallel with a second transistor between a master latch circuit and a slave latch circuit, wherein the first transistor is controlled by the first local clock signal and the second transistor is controlled by the second local clock signal.

13. The multi-bit flip-flop of claim 1 , wherein each of the plurality of local control signals is provided to each of the input data selection circuits.

14. A method of operating a multi-bit flip-flop comprising:
generating a plurality of local control signals, wherein each of the local control signals is generated in response to both a global clock signal and a global scan enable signal; and
applying each of the plurality of local control signals to a plurality of input data selection circuits of a corresponding plurality of flip-flops, wherein the local control signals exclusively control each of the input data selection circuits to selectively route one of a corresponding input data value and a corresponding scan input data value as a master data value.

15. The method of claim 14 , further comprising storing the master data value in a master latch circuit in response to the local control signals.

16. The method of claim 15 , further comprising:
generating local clock signals in response to the global clock signal; and
transferring the master data value from the master latch circuit to a slave latch circuit, wherein the transferring is controlled exclusively by the local clock signals.

17. The method of claim 15 , further comprising
generating a local reset control signal in response to both the global reset signal and the global clock signal; and
resetting the master latch circuit in response to the local reset control signal.

18. The method of claim 14 , wherein generating the plurality of local control signals comprises:
generating a first local clock signal in response to the global clock signal;
generating a local scan enable signal in response to the global scan enable signal;
performing a logical NAND operation in response to the first local clock signal and the local scan enable signal to provide a first local control signal; and
performing a logical NAND operation in response to the first local clock signal and the global scan enable signal to provide a second local control signal.

19. The method of claim 18 , further comprising:
inverting the first local control signal to provide a third local control signal; and

Assignees

• Synopsys Inc

Inventors

• Srivastava Manish
• Reddy Basannagouda Somanath

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K3/35625

  using complementary field-effect transistors · CPC title