Vertical semiconductor pillar device

Patent metadata

Field	Value
Publication number	US-9728634-B2
Application number	US-201615003246-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Nov 29, 2012
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.

First claim

What is claimed is:

1. An apparatus comprising:
a first dielectric material extending from a surface supported by a substrate, the first dielectric material forming multiple spaced walls;
a second dielectric material extending from the surface supported by the substrate, and forming multiple dielectric pillars extending between respective pairs of the multiple spaced walls of the first dielectric material; and
a vertical device comprising,
a semiconductor pillar, the semiconductor pillar extending from the surface supported by the substrate and in contact with a wall of the first dielectric material and a dielectric pillar of the second dielectric material, and
a vertical gate material formed over a first portion of a side of the semiconductor pillar and over a portion of a side of the dielectric pillar of the second dielectric material.

2. The apparatus of claim 1 , wherein:
the first dielectric material comprises silicon nitride;
the second dielectric material comprises silicon dioxide; and
the substrate comprises a silicon substrate; and
wherein the wall of the first dielectric material is in contact with a respective dielectric pillar of the second dielectric material.

3. The apparatus of claim 1 , wherein the semiconductor pillar comprises selective epitaxially grown silicon, and wherein at least a lower portion of the sides of the semiconductor pillar contacts both the first and second dielectric materials.

4. The apparatus of claim 1 , wherein the vertical device comprises a metal oxide semiconductor field effect transistor.

5. The apparatus of claim 1 , wherein the vertical device comprises a thyristor.

6. The apparatus of claim 1 , wherein the apparatus comprises a system.

7. The apparatus of claim 1 , wherein the apparatus comprises a memory device.

8. The apparatus of claim 7 , wherein the memory device comprises a NOT AND (NAND) memory device.

9. The memory device of claim 1 , wherein the surface supported by a substrate includes the surface of the substrate.

10. The memory device of claim 1 , wherein the surface supported by a substrate includes an insulator formed over the substrate.

11. The memory device of claim 1 , wherein the surface supported by a substrate is a doped silicon surface of the substrate.

12. A memory device comprising:
a first dielectric material above a substrate;
a second dielectric material above the substrate, and in contact with the first dielectric material;
a vertical semiconductor structure comprising,
a pillar, a lower portion of the pillar in contact with both the first dielectric material and the second dielectric material, the first and second dielectric materials extending alongside the vertical semiconductor structure;
a gate dielectric material on the second dielectric material, a side of the pi r of the vertical semiconductor structure, and a side of the first dielectric material;
a vertical gate material on a first portion of the gate dielectric material formed on the side of the vertical semiconductor structure and on the gate dielectric material formed on the second dielectric material; and
a third dielectric material on a second portion of the gate dielectric material on the side of the vertical semiconductor structure.

13. The memory device of claim 12 , wherein the third dielectric material is formed between the vertical gate material and a second vertical gate material formed on a side of an adjacent vertical semiconductor structure.

14. The memory device of claim 12 , wherein the first dielectric material is a silicon nitride material.

15. The memory device of claim 12 , wherein the second dielectric material silicon dioxide.

16. A memory device comprising:
a first wall of a first dielectric material above a substrate;
a second wall of the first dielectric material above the substrate and extending in spaced parallel relation to the first wall;
a first pillar of a second dielectric material above the substrate and between and contacting both the first and second walls;
a vertical semiconductor device extending between and in contact with the first and second walls and the first pillar of the second dielectric material, wherein the vertical semiconductor device comprises:
a semiconductor pillar;
a vertical gate material formed over a first portion of a side of the semiconductor pillar and over the pillar of second dielectric material; and
a dielectric material formed on the gate material and on a second portion of the side of the semiconductor pillar.

17. The memory device of claim 16 , further comprising:
a second pillar of the second dielectric material extending between and in contact with the first and second walls and in spaced relation to the first pillar of a second dielectric material; and
a plurality of vertical semiconductor devices, each vertical device extending between and in contact with the first and second walls and at least one of the first and second pillars of second dielectric material.

18. The memory device of claim 16 , wherein the vertical semiconductor device comprises a pillar of epitaxially grown silicon on the substrate.

19. The memory device of claim 18 , wherein the pillar of epitaxially grown silicon comprises a pillar of selective grown epitaxial silicon (SEG).

20. The memory device of claim 16 , wherein the vertical device further comprises a metal oxide semiconductor field effect transistor.

21. The memory device of claim 16 , wherein the vertical device is self-aligned with the first dielectric material and the second dielectric material.

22. The memory device of claim 16 , wherein the second dielectric material comprises alumina.

Assignees

• Micron Technology Inc

Inventors

• Mariani Marcello
• Pozzi Carlo

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H01L27/10805

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/495

  Electricity · mapped topic

• H01L29/7889

  Electricity · mapped topic