Semiconductor devices and fabrication methods

Patent metadata

Field	Value
Publication number	US-9245987-B2
Application number	US-201213689442-A
Country	US
Kind code	B2
Filing date	Nov 29, 2012
Priority date	Nov 29, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.

First claim

What is claimed is:

1. A method comprising:
forming a first dielectric material on a substrate;
removing a portion of the first dielectric material to leave a remainder of the first dielectric material on the substrate;
forming a second dielectric material on the substrate in contact with the remainder of the first dielectric material;
removing a portion of the second dielectric material to leave a remainder of the second dielectric material in contact with the remainder of the first dielectric material;
forming a vertical semiconductor structure in contact with the remainder of the first dielectric material and the remainder of the second dielectric material;
forming a gate dielectric material on the remainder of the second dielectric material, a side of the vertical semiconductor structure, and a side of the remainder of the first dielectric material;
forming a vertical gate material on a first portion of the gate dielectric material formed on the side of the vertical semiconductor structure and on the ate dielectric material formed on the remainder of the second dielectric material; and
forming a third dielectric material on a second portion of the gate dielectric material on the side of the vertical semiconductor structure.

2. The method of claim 1 , further comprising:
forming the third dielectric material between the vertical gate material and a second vertical gate material formed on a side of an adjacent vertical semiconductor structure.

3. The method of claim 1 , wherein removing a portion of the second dielectric material further comprises etching the second dielectric material to remove the portion of the second dielectric material.

4. The method of claim 1 , wherein forming the first dielectric material further comprises forming silicon nitride.

5. The method of claim 1 , wherein forming the second dielectric material further comprises forming silicon dioxide.

6. The method of claim 1 , wherein removing a portion of the first dielectric material further comprises etching the first dielectric material.

7. The method of claim 1 , wherein forming the vertical semiconductor structure further comprises forming a vertical silicon structure in contact with the remainder of the first dielectric material and the remainder of the second dielectric material.

8. A method comprising:
forming a first dielectric material on a substrate;
etching the first dielectric material to form a first void in the first dielectric material;
forming a second dielectric material in the first void in the first dielectric material;
etching the first dielectric material to form a second void extending to the second dielectric material;
forming a vertical semiconductor device at least partially in the second void;
wherein forming the vertical semiconductor device comprises:
forming a semiconductor pillar in the second void;
forming a vertical gate material over a first portion of a side of the semiconductor pillar and over the second dielectric material; and
forming a dielectric material on the vertical gate material and on a second portion of the side of the semiconductor pillar.

9. The method of claim 8 , wherein:
etching the first dielectric material to form a first void further comprises etching the first dielectric material to form a plurality of first voids in the first dielectric material; and
etching the first dielectric material to form a second void further comprises etching the first dielectric material to form a plurality of second voids extending to the second dielectric material; and
forming the vertical device further comprises forming a respective vertical device at least partially in each of the second voids.

10. The method of claim 8 , wherein forming the vertical device further comprises selectively growing epitaxial silicon on the substrate to form a pillar of selective epitaxial grown silicon.

11. The method of claim 8 , wherein forming the vertical device further comprises forming a metal oxide semiconductor field effect transistor at least partially in the second void.

12. The method of claim 8 , wherein forming the vertical device further comprises forming a vertical thyristor at least partially in the second void.

13. The method of claim 8 , wherein:
etching the first dielectric material further comprises wet etching or dry etching silicon nitride; and
etching the second dielectric material further comprises wet etching or dry etching silicon dioxide.

14. A method comprising:
forming a first dielectric material on a substrate;
forming a second dielectric material on the substrate or on the first dielectric material; and
growing epitaxial semiconductor material on the substrate in contact with the first dielectric material and the second dielectric material to form a vertical device, wherein forming the vertical device comprises:
forming a gate oxide on a side of the semiconductor material and on the second dielectric material;
forming a vertical metal gate material on the gate oxide of a first portion of the side of the semiconductor material and on the ate oxide of the second dielectric material; and
forming a dielectric material on the vertical metal gate material and on the gate oxide of a second portion of the side of the semiconductor pillar.

15. The method of claim 14 , wherein growing epitaxial semiconductor material further comprises doping the epitaxial semiconductor material as it is being grown.

16. The method of claim 14 , wherein growing epitaxial semiconductor material further comprises selectively growing epitaxial silicon to form a pillar of selective epitaxial grown (SEG) silicon on the substrate.

17. The method of claim 14 , wherein growing epitaxial semiconductor material further comprises growing the epitaxial semiconductor material to be self-aligned with the first dielectric material and the second dielectric material.

18. The method of claim 14 , further comprising:
etching the first dielectric material without etching the second dielectric material; and
etching the second dielectric material without etching the first dielectric material.

19. The method of claim 18 , wherein etching the second dielectric material further comprises etching the second dielectric material with a self-aligned etch.

20. The method of claim 14 , wherein growing epitaxial semiconductor material further comprises growing the epitaxial semiconductor material on the substrate in contact with the first dielectric material in a first direction and in contact with the second dielectric material in a second direction.

21. The method of claim 14 , wherein:
forming the first dielectric material further comprises forming silicon dioxide on the substrate; and
forming the second dielectric material further comprises forming polysilicon on the substrate.

22. The method of claim 14 , wherein:
forming the first dielectric material further comprises forming silicon dioxide on the substrate; and
forming the second dielectric material further comprises forming alumina on the substrate.

23. The method of claim 14 , wherein:
forming the first dielectric material further comprises forming silicon nitride on the substrate; and
forming the second dielectric material further comprises forming silicon dioxide on the substrate.

24. A method comprising:
forming a first dielectric material on a substrate;
etching the first dielectric material to form a plurality of first voids in the first dielectric

Assignees

• Micron Technology Inc

Inventors

• Mariani Marcello
• Pozzi Carlo

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title