Semiconductor device with self-aligned contact plugs

Patent metadata

Field	Value
Publication number	US-9355957-B2
Application number	US-201514685823-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Jun 18, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device includes subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure including a gate electrode dielectrically insulated from the semiconductor portion. The semiconductor device further includes alignment plugs in a vertical projection of the subsurface structures, contact spacers extending along sidewalls of the alignment plugs tilted to the main surface, and contact plugs directly adjoining semiconductor mesas between the subsurface structures. The contact plugs are provided between opposing ones of the contact spacers.

First claim

What is claimed is:

1. A semiconductor device, comprising:
subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure comprising a gate electrode dielectrically insulated from the semiconductor portion;
alignment plugs in a vertical projection of the subsurface structures;
contact spacers extending along sidewalls of the alignment plugs tilted to the main surface; and
contact plugs directly adjoining semiconductor mesas between the subsurface structures, the contact plugs provided between opposing ones of the contact spacers;

wherein the alignment plugs comprise (i) gate contact spacers of a first auxiliary material along sidewalls of the contact spacer opposite to the contact plugs and (ii) gate contacts between the gate contact spacers assigned to a respective subsurface structure.

2. The semiconductor device of claim 1 , further comprising:
source zones of a first conductivity type in the semiconductor mesas directly adjoining the main surface.

3. The semiconductor device of claim 1 , further comprising:
body zones of a complementary second conductivity type in the semiconductor mesas, the body zones forming first pn junctions with the source zones and second pn junctions with a drift layer of the first conductivity type.

Assignees

• Infineon Technologies Austria

Inventors

• Poelzl Martin

Classifications

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title