TFT array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-9728557-B2
Application number	US-201414226775-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Oct 10, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A TFT array substrate is disclosed. The TFT array substrate includes a substrate, a data line disposed above the substrate, and a gate insulating layer disposed above the substrate, where the gate insulating layer includes a groove. The TFT array substrate also includes a data line disposed within the groove of the gate insulating layer.

First claim

What is claimed is:

1. A TFT array substrate, comprising:
a substrate;
a plurality of gate lines formed on the substrate;
a gate insulating layer disposed on the plurality of gate lines;
a plurality of grooves formed in the gate insulating layer;
a plurality of data lines each disposed inside one of the plurality of grooves, wherein the data lines are insulated from the said gate lines, wherein a projection of the data lines and a projection of the gate lines onto the substrate intersect with each other, and the data lines and the gate lines define an array of pixel units;
a dielectric layer disposed on the gate insulating layer; and
a common electrode disposed on the dielectric layer;
wherein the grooves are completely covered by the orthogonal projection of the common electrodes onto the substrate.

2. The TFT array substrate of claim 1 , wherein the plurality of grooves are cutting through the gate insulating layer to expose the substrate.

3. The TFT array substrate of claim 1 , wherein the plurality of grooves are partially embedded in the gate insulating layer.

4. The TFT array substrate of claim 3 , wherein the grooves opens to a side away from the substrate.

5. The TFT array substrate of claim 3 , wherein the grooves opens to a side facing the substrate.

6. The TFT array substrate of claim 5 , further comprising:
a conducting line; and
connecting via holes,
wherein the conducting line is disposed on the gate insulating layer, the connecting via holes extend through the gate insulating layer toward the substrate, and the conducting line is connected with the data line through the connecting via holes.

7. The TFT array substrate of claim 1 , further comprising a gate line between the substrate and the gate insulating layer, wherein the grooves does not intersect with the gate line in a plane view.

8. The TFT array substrate of claim 1 , wherein each of the grooves includes two end sides extending across the data line, and each of the end sides is spaced from an adjacent gate line by a distance greater than 4 μm.

9. The TFT array substrate of claim 1 , wherein each of the grooves includes two lateral sides extending lengthwise on opposite sides next to a respective data line, and each of the lateral sides is spaced from the data line by a distance greater than 2 μm.

10. The TFT array substrate of claim 1 , wherein a cross-sectional shape of the grooves are a trapezoid or a parallelogram.

11. The TFT array substrate of claim 1 , wherein the data line has a first surface on a side distal from the substrate, the common electrode has a second surface on a side proximal to the substrate, and a distance between the first surface of the data line and the second surface of the common electrode is greater than 1.5 μm.

12. The TFT array substrate of claim 1 , further comprising a pixel electrode disposed below the common electrode.

13. The TFT array substrate of claim 12 , wherein at least one of the pixel electrode and the common electrode is in a shape of comb-teeth.

14. The TFT array substrate of claim 1 , further comprising a pixel electrode, wherein the pixel electrode is disposed above the common electrode.

15. A display panel, comprising:
a color filter substrate, and
a TFT array substrate disposed opposite to the color filter substrate, the TFT array substrate comprising:
a substrate;
a plurality of gate lines formed on the substrate;
a gate insulating layer disposed on the plurality of gate lines;
a plurality of grooves formed in the gate insulating layer;
a plurality of data lines each disposed inside one of the plurality of grooves, wherein the data lines are insulated from the said gate lines, wherein a projection of the data lines and a projection of the gate lines onto the substrate intersect with each other, and the data lines and the gate lines define an array of pixel units;
a dielectric layer disposed on the gate insulating layer; and
a common electrode layer disposed on the dielectric layer;
wherein the grooves are completely covered by the orthogonal projection of the common electrodes on the substrate.

16. The TFT array substrate of claim 15 , further comprising a pixel electrode, wherein the pixel electrode is disposed above the common electrode.

17. A display device, comprising:
a display panel, which comprises,
a TFT array substrate, comprising:
a substrate;
a plurality of gate lines formed on the substrate;
a gate insulating layer disposed on the plurality of gate lines;
a plurality of grooves formed in the gate insulating layer;
a plurality of data lines each disposed inside one of the plurality of grooves, wherein the data lines are insulated from the said gate lines, wherein a projection of the data lines and a projection of the gate lines onto the substrate intersect with each other, and the data lines and the gate lines define an array of pixel units;
a dielectric layer disposed on the gate insulating layer; and
a common electrode layer disposed on the dielectric layer;
wherein the grooves are completely covered by the orthogonal projection of the common electrodes onto the substrate.

18. The TFT array substrate of claim 17 , further comprising a pixel electrode, wherein the pixel electrode is disposed above the common electrode.

Assignees

• Shanghai Avic Optoelectronics
• Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Wang Tinghai
• Cao Zhaokeng

Classifications

• H01L27/1248

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title