Liquid crystal display device and method of manufacturing the same

US9104081B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9104081-B2
Application numberUS-201313855026-A
CountryUS
Kind codeB2
Filing dateApr 2, 2013
Priority dateNov 20, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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A liquid crystal device including an array substrate facing an opposite substrate; and a liquid crystal layer between the array and opposite substrate, the array substrate including a gate electrode and gate line on a base substrate; a gate insulating layer covering the gate electrode and including a trench crossing the gate line; a semiconductor layer on the gate insulating layer and including a channel area overlapping the gate electrode, a source area at one side of the channel area, and a drain area at another side of the channel area; a pixel electrode on the gate insulating layer and spaced apart from the semiconductor layer; a source electrode connected to the source area; a drain electrode connected to the drain area and the pixel electrode; a data line connected to the source electrode and being inside the trench; and a common electrode insulated from the pixel electrode.

First claim

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What is claimed is: 1. A liquid crystal display device, comprising: an array substrate; an opposite substrate facing the array substrate; and a liquid crystal layer between the array substrate and the opposite substrate, wherein the array substrate includes: a base substrate; a gate electrode and a gate line on the base substrate; a gate insulating layer covering the gate electrode, the gate insulating layer including a trench crossing the gate line; a semiconductor…

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What does patent US9104081B2 cover?
A liquid crystal device including an array substrate facing an opposite substrate; and a liquid crystal layer between the array and opposite substrate, the array substrate including a gate electrode and gate line on a base substrate; a gate insulating layer covering the gate electrode and including a trench crossing the gate line; a semiconductor layer on the gate insulating layer and including…
Who is the assignee on this patent?
Ahn Hyun Jae, Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136286. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).