Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016133642-A1
Application number	US-201514694829-A
Country	US
Kind code	A1
Filing date	Apr 23, 2015
Priority date	Nov 11, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

2 . The semiconductor device according to claim 1 , wherein a lower part of the first channel region is coupled to a lower part of the second channel region.

3 . The semiconductor device according to claim 1 , further comprising:
a drain selection line (DSL) formed below the memory cell structure; and a source selection line (SSL) formed over the memory cell structure.

4 . The semiconductor device according to claim 1 , further comprising:
a source line formed over the memory cell structure, coupled to the first channel region at both sides of the first channel region, and extended parallel to the memory cell structure.

5 . The semiconductor device according to claim 1 , further comprising:
a bit line coupled to an upper part of the second channel region, and extended perpendicular to the memory cell structure.

6 . The semiconductor device according to claim 1 , wherein the memory cell structure is formed by alternately stacking an insulation film and a word line over the semiconductor substrate.

7 . The semiconductor device according to claim 6 , wherein the word line includes polysilicon or metal.

8 . The semiconductor device according to claim 1 , further comprising:
a charge storage region formed over the sidewalls of the through-hole, and disposed between the memory cell structure and the first channel region.

9 . The semiconductor device according to claim 8 , wherein the charge storage region includes an oxide-nitride-oxide (ONO) dielectric layer.

Assignees

• Sk Hynix Inc

Inventors

• Jeon Jae Eun
• Oh Sung Lae

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H10B41/30 Primary

  characterised by the memory core region · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title