Methods of fabricating semiconductor devices including fin-shaped active regions

Patent metadata

Field	Value
Publication number	US-9728535-B2
Application number	US-201615058664-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Feb 8, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of fins protruding from the substrate; and
a plurality of device insulating layers, each of the plurality of device insulating layers being disposed between corresponding two adjacent fins among the plurality of fins,
wherein at least one of the plurality of fins includes a shoulder portion disposed between a bottom surface of a corresponding adjacent device insulating layer and a top surface of the at least one of the plurality of fins, and
the at least one of the plurality of fins includes an upper portion and a lower portion that is wider than the upper portion, and wherein:
the plurality of device insulating layers include a first group of device insulating layers and a second group of device insulating layers;
the plurality of device insulating layers include a first device insulating layer disposed between two adjacent device insulating layers in the first group, a second device insulating layer disposed between two adjacent device insulating layers in the second group, and a third device insulating layer disposed between the first group and the second group; and
a depth of the third device insulating layer is greater than a depth of the first device insulating layer and greater than a depth of the second device insulating layer.

2. The semiconductor device of claim 1 , further comprising a plurality of liner insulating layers, each of the plurality of liner insulating layers being disposed between corresponding two adjacent fins among the plurality of fins.

3. The semiconductor device of claim 1 , wherein the first device insulating layer contacts the shoulder portion, and
the third device insulating layer does not contact the shoulder portion.

4. The semiconductor device of claim 1 , wherein a distance between the two adjacent device insulating layers in the first group is different from a distance between the two adjacent device insulating layers in the second group.

5. The semiconductor device of claim 1 , wherein a distance between the two adjacent device insulating layers in the first group is a same distance as a distance between the two adjacent device insulating layers in the second group.

6. The semiconductor device of claim 1 , wherein a number of device insulating layers in the first group is different from a number of device insulating layers in the second group.

7. The semiconductor device of claim 1 , wherein a distance between two outermost device insulating layers in the first group is different from a distance between two outermost device insulating layers in the second group.

8. The semiconductor device of claim 1 , wherein the at least one of the plurality of fins includes a sidewall that has a first portion and a second portion, each of the first portion and the second portion being disposed higher than the shoulder portion, and
a slope of the first portion of the sidewall is different from a slope of the second portion of the sidewall.

9. A semiconductor device comprising:
a substrate;
a plurality of fins protruding from the substrate; and
a plurality of device insulating layers, each of the plurality of device insulating layers being disposed between corresponding two adjacent fins among the plurality of fins,
wherein at least one of the plurality of fins includes a shoulder portion disposed between a bottom surface of a corresponding adjacent device insulating layer and a top surface of the at least one of the plurality of fins,
the shoulder portion includes an upwardly protruding portion, and
at least one of the plurality of device insulating layers includes a lower portion and an upper portion that is wider than the lower portion,
wherein ones of the plurality of device insulating layers divide the plurality of fins into respective fin groups having different pitches.

10. The semiconductor device of claim 9 , further comprising a plurality of liner insulating layers, each of the plurality of liner insulating layers being disposed between corresponding two adjacent fins among the plurality of fins.

11. The semiconductor device of claim 10 , wherein each of the plurality of device insulating layers is disposed on a corresponding liner insulating layer among the plurality of liner insulating layers.

12. The semiconductor device of claim 9 , further comprising a plurality of covering insulating layers, each of the plurality of covering insulating layers covering a top portion of each of the plurality of fins, the top portion of each of the plurality of fins being above top surfaces of adjacent device insulating layers among the plurality of device insulating layers such that each of the plurality of fins protrudes from the top surfaces of the adjacent device insulating layers by a uniform distance.

13. The semiconductor device of claim 9 , wherein the plurality of device insulating layers include a first device insulating layer, a second device insulating layer and a third device insulating layer, the first device insulating layer being adjacent to the second device insulating layer, the third device insulating layer being adjacent to the second device insulating layer, and
a shortest distance between the first device insulating layer and the second device insulating layer is less than a shortest distance between the second device insulating layer and the third device insulating layer.

14. The semiconductor device of claim 9 , wherein the plurality of device insulating layers include a first device insulating layer, a second device insulating layer and a third device insulating layer, the first device insulating layer being adjacent to the second device insulating layer, the third device insulating layer being adjacent to the second device insulating layer, and
a shortest distance between the first device insulating layer and the second device insulating layer is a same distance as a shortest distance between the second device insulating layer and the third device insulating layer.

15. A semiconductor device comprising:
a substrate;
a plurality of fins protruding from the substrate;
a plurality of liner insulating layers, each of the plurality of liner insulating layers being disposed between corresponding two adjacent fins among the plurality of fins; and
a plurality of device insulating layers, each of the plurality of device insulating layers being disposed between corresponding two adjacent fins among the plurality of fins,
wherein at least one of the plurality of fins includes a sidewall that has a first portion and a second portion,
a slope of the first portion of the sidewall is different from a slope of the second portion of the sidewall,
the sidewall of the at least one of the plurality of fins includes a convexly protruding portion, and
the at least one of the plurality of fins includes an upper portion and a lower portion that is wider than the upper portion,
wherein ones of the plurality of device insulating layers divide the plurality of fins into respective fin groups having different pitches.

16. The semiconductor device of claim 15 wherein the plurality of liner insulating layers include polysilicon, and the plurality of device insulating layers include oxide.

17. The semiconductor device of claim 15 , further comprising a plurality of gate insulating layers covering the plurality of fins and contacting an upper surface of the plurality of liner insulating layers.

18. The semiconductor device of claim 15 , wherein the convexly protruding portion of the sidewall of the at least one of the plurality o

Assignees

• Youn Young-Sang
• Song Myung-Geun
• Cha Ji-Hoon
• Baek Jae-Jik
• Yoon Bo-Un
• Han Jeong-Nam
• Samsung Electronics Co Ltd

Inventors

• Youn Young-Sang
• Song Myung-Geun
• Cha Ji-Hoon
• Baek Jae-Jik
• Yoon Bo-Un
• Han Jeong-Nam

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title