System with a high power chip and a low power chip having low interconnect parasitics

Patent metadata

Field	Value
Publication number	US-9728481-B2
Application number	US-201113227328-A
Country	US
Kind code	B2
Filing date	Sep 7, 2011
Priority date	Sep 7, 2011
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An IC system includes low-power chips, e.g., memory chips, located proximate one or more higher power chips, e.g., logic chips, without suffering the effects of overheating. The IC system may include a high-power chip disposed on a packaging substrate and a low-power chip embedded in the packaging substrate to form a stack. Because portions of the packaging substrate thermally insulate the low-power chip from the high-power chip, the low-power chip can be embedded in the IC system in close proximity to the high-power chip without being over heated by the high-power chip. Such close proximity between the low-power chip and the high-power chip advantageously shortens the path length of interconnects therebetween, which improves device performance and reduces interconnect parasitics in the IC system.

First claim

We claim:

1. A system, comprising:
a first high-power chip disposed on a first side of a chip-packaging substrate;
a first thermally insulating layer and a second thermally insulating layer;
a first low-power chip embedded in the chip-packaging substrate between the first thermally insulating layer and the second thermally insulating layer and electrically connected to the first high-power chip, and
a heat-distribution layer that includes one or more layers of metallic foil and is embedded in the chip-packaging substrate between the first thermally insulating layer and the second thermally insulating layer and adjacent to the first low-power chip, wherein the heat-distribution layer extends from a first edge of the chip-packaging substrate to a second edge of the chip packaging substrate and does not substantially vary in depth,
wherein the high-power chip generates at least 10 W of heat and the low-power chip generates less than 5 W of heat.

2. The system of claim 1 , wherein the first low-power chip is electrically connected to the first high-power chip by a through-silicon via formed in the first low-power chip.

3. The system of claim 1 , wherein at least one of the first thermally insulating layer and the second thermally insulating layer comprises a thermally insulating material having a thermal conductivity of less than about 0.5 W/(° C.-m).

4. The system of claim 1 , wherein the first low-power chip comprises a memory chip.

5. The system of claim 1 , wherein the first low-power chip is disposed between the first high-power chip and a plurality of electrical leads that are configured to electrically connect the system to a printed circuit board.

6. The system of claim 1 , further comprising a second low-power chip that is embedded in the chip-packaging substrate.

7. The system of claim 1 , wherein the heat-distribution layer is positioned between the first high-power chip and the first low-power chip.

8. The system of claim 2 , wherein the heat-distribution layer includes a plurality of through-holes, and the through-silicon via passes through one of the plurality of through-holes.

9. The system of claim 1 , wherein the heat-distribution layer is disposed between the first low-power chip and the first thermally insulating layer.

10. The system of claim 9 , wherein the second thermally insulating layer is disposed between the first low-power chip and a second low-power chip.

Assignees

• Yee Abraham F
• Greco Joe
• Zhai Jun
• Minacapelli Joseph
• Chen John Y
• Nvidia Corp

Inventors

• Yee Abraham F
• Greco Joe
• Zhai Jun
• Minacapelli Joseph
• Chen John Y

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title