Space-efficient underfilling techniques for electronic assemblies

US9728425B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9728425-B1
Application numberUS-201615089491-A
CountryUS
Kind codeB1
Filing dateApr 2, 2016
Priority dateApr 2, 2016
Publication dateAug 8, 2017
Grant dateAug 8, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: mounting an electronic element on a surface of a substrate; dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, the underfill material to comprise a non-visible light (NVL)-curable material; and projecting curing rays upon a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region into a keep-out-zone while allowing the dispensed underfill material to flow within the dispense region. 2. The method of claim 1 , the curing rays to comprise ultraviolet (UV) light. 3. The method of claim 1 , the curing rays to comprise infrared (IR) light. 4. The method of claim 1 , comprising conveying a dispense assembly along a dispense path to dispense the underfill material within the dispense region. 5. The method of claim 4 , the dispense assembly to comprise a light source, the light source to project a curing beam upon at least a portion of the dispensed underfill material as the dispense assembly traverses the dispense path. 6. The method of claim 1 , comprising projecting a curing frame upon a curing region surrounding the dispense region, the curing region to correspond to the keep-out-zone. 7. The method of claim 1 , the electronic element to comprise a semiconductor die. 8. The method of claim 7 , the semiconductor die to comprise one or more integrated circuits (ICs). 9. The method of claim 1 , the substrate to comprise a printed circuit board (PCB). 10. The method of claim 1 , the underfill material to comprise an NVL-curable epoxy. 11. A method, comprising: projecting curing rays onto a substrate to form a curing frame to define a dispense region within the curing frame and keep-out-zone; and dispensing an underfill material onto the substrate in the dispense region to form an underfill for an electronic element, the underfill material to comprise a non-visible light (NVL)-curable material, the curing rays to inhibit an outward flow of dispensed underfill material from the dispense region into the keep-out-zone while allowing the dispensed underfill material to flow within the dispense region. 12. The method of claim 11 , the curing rays to comprise ultraviolet (UV) light. 13. The method of claim 11 , the curing rays to comprise infrared (IR) light. 14. The method of claim 11 , the electronic element to comprise a semiconductor die. 15. The method of claim 14 , the semiconductor die to comprise one or more integrated circuits (ICs). 16. The method of claim 11 , the substrate to comprise a printed circuit board (PCB). 17. The method of claim 11 , the underfill material to comprise an NVL-curable epoxy.

Assignees

Inventors

Classifications

  • Housings or casings incorporating or embedding electric or electronic elements · CPC title

  • Use of {EP, i.e.} epoxy resins {or derivatives thereof}, as moulding material · CPC title

  • Conductive · CPC title

  • Apparatus for sealing, encapsulating, glassing, decapsulating or the like · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

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What does patent US9728425B1 cover?
Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W74/012. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 08 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).