Method for manufacturing a semiconductor wafer, and semiconductor device having a low concentration of interstitial oxygen

Patent metadata

Field	Value
Publication number	US-9728395-B2
Application number	US-201514867839-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Oct 9, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method for manufacturing a substrate wafer 100 includes providing a device wafer ( 110 ) having a first side ( 111 ) and a second side ( 112 ); subjecting the device wafer ( 110 ) to a first high temperature process for reducing the oxygen content of the device wafer ( 110 ) at least in a region ( 112 a ) at the second side ( 112 ); bonding the second side ( 112 ) of the device wafer ( 110 ) to a first side ( 121 ) of a carrier wafer ( 120 ) to form a substrate wafer ( 100 ); processing the first side ( 101 ) of the substrate wafer ( 100 ) to reduce the thickness of the device wafer ( 110 ); subjecting the substrate wafer ( 100 ) to a second high temperature process for reducing the oxygen content at least of the device wafer ( 110 ); and at least partially integrating at least one semiconductor component ( 140 ) into the device wafer ( 110 ) after the second high temperature process.

First claim

The invention claimed is:

1. A method for manufacturing a substrate wafer, the method comprising:
providing a device wafer having a first side and a second side opposite the first side, the device wafer being made of a semiconductor material and having a first thickness;
subjecting the device wafer to a first high temperature process for reducing the oxygen content of the device wafer at least in a region at the second side;
bonding the second side of the device wafer to a first side of a carrier wafer to form a substrate wafer comprising the device wafer bonded to the carrier wafer, the carrier wafer having a second side opposite the first side which second side of the carrier wafer forms the second side of the substrate wafer, wherein the first side of the device wafer forms a first side of the substrate wafer;
processing the first side of the substrate wafer, which is formed by the first side of the device wafer, to reduce the thickness of the device wafer to a second thickness less than the first thickness of the device wafer;
subjecting the substrate wafer to a second high temperature process for reducing the oxygen content at least of the device wafer bonded to the carrier wafer;
at least partially integrating at least one semiconductor component into the device wafer after the second high temperature process.

2. The method of claim 1 , further comprising:
forming an oxygen barrier on at least one of the second side of the device wafer and the first side of the carrier wafer prior to bonding the device wafer to the carrier wafer.

3. The method of claim 1 , further comprising:
subjecting the carrier wafer to a third high temperature process for reducing the oxygen content of the carrier wafer prior to bonding the device wafer to the carrier wafer.

4. The method of claim 1 , wherein providing the device wafer comprises providing the device wafer having an initial interstitial oxygen concentration of equal to or less than 5*10 17 /cm 3 .

5. The method of claim 1 , wherein the first thickness of the device wafer is 300 μm to 850 μm.

6. The method of claim 1 , wherein the second thickness of the device wafer is less than 400 μm.

7. The method of claim 1 , further comprising:
processing a rim of the device wafer after reducing the thickness of the device wafer.

8. The method of claim 1 , further comprising:
removing the carrier wafer after at least partially integrating the semiconductor component.

9. The method of claim 1 , wherein each of the device wafer and of the carrier wafer has a diameter of at least 150 mm, particularly of at least 200 mm.

10. The method of claim 1 , further comprising:
forming an oxide layer on at least one of the first and second side of the device wafer; and
removing the oxide layer prior to subjecting the device wafer to the first high temperature process.

11. The method of claim 1 , further comprising:
forming at least one of an epitaxial layer and a doped region on the second side of the device wafer prior to bonding the device wafer to the carrier wafer.

12. The method of claim 1 , further comprising:
forming a doping region at the first side of the carrier wafer prior to bonding the device wafer to the carrier wafer.

13. The method of claim 1 , wherein the carrier wafer comprises a semiconductor material.

Assignees

• Infineon Technologies Ag

Inventors

• Oefner Helmut
• Caspary Nico
• Momeni Mohammad
• Ploss Reinhard
• Santos Rodriguez Francisco Javier
• Schulze Hans-Joachim

Classifications

• H10P95/902

  for the formation of PN junctions without addition of impurities · CPC title

• H10P36/03

  within silicon bodies · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D64/01352

  with sacrificial oxide · CPC title