Semiconductor memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9147484-B2
Application number	US-201414200454-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Sep 26, 2013
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A semiconductor memory device and an operating method thereof are provided. The semiconductor memory device includes a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells, a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells, and a control logic suitable for controlling the voltage generator to generate the pass voltage to have different levels depending on a distance between the drain-select transistor and the selected memory cell during a read operation.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory groups each including at least a drain-select transistor and a plurality of memory cells;
a voltage generator suitable for generating a read voltage that is to be applied to a selected memory cell of the memory cells and a pass voltage that is to be applied to unselected memory cells other than the selected memory cell among the memory cells; and
a control logic…

Assignees

• Sk Hynix Inc

Inventors

• Choi Sung Dae

Classifications

• G11C16/26 Primary

  Physics · mapped topic

• G11C16/30

  Physics · mapped topic

• G11C16/0483

  Physics · mapped topic

• G11C16/3418

  Physics · mapped topic

• G11C16/06

  Physics · mapped topic