Method and apparatus for stream buffer management instructions

Patent metadata

Field	Value
Publication number	US-9727471-B2
Application number	US-95576310-A
Country	US
Kind code	B2
Filing date	Nov 29, 2010
Priority date	Nov 29, 2010
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

First claim

What is claimed is:

1. A processor comprising:
an instruction fetch unit to fetch an instruction of an instruction set of the processor, the instruction having a format that includes a first parameter to indicate a source memory address, a second parameter to indicate a different destination memory address which is different than the source memory address, and a third parameter to specify a memory hierarchy level for the destination memory address; and
an execution unit to perform the instruction, wherein the execution unit to perform the instruction is to:
perform a first operation to read data from the source memory address into a buffer of the processor without allocating a cache memory line to store the data; and
perform a second operation to allocate a cache memory line at the destination memory address, and to store the data from the buffer of the processor to the allocated cache memory line, wherein the cache memory line is to be allocated in a cache memory that is to be based at least in part on the memory hierarchy level that is to be specified by the third parameter of the instruction.

2. The processor of claim 1 , wherein the execution unit to perform the instruction to read the data from the source memory address is to:
determine whether the data of the source memory address is stored in one of one or more cache memories; and
in response to a determination that the data of the source memory address is stored in said one of the one or more cache memories, copy the data of the source memory address from said one cache memory to the buffer.

3. The processor of claim 1 , wherein the buffer comprises a register.

4. The processor of claim 1 , wherein a width of the data comprises one of a byte width, 32 bytes width, 64 bytes width, 128 bytes width, and a vector register width.

5. The processor of claim 1 , wherein the instruction is to indicate a plurality of source memory addresses.

6. The processor of claim 1 , wherein the data is to be read from a main memory into the buffer.

7. The processor of claim 1 , wherein the buffer is in a core of the processor.

8. The processor of claim 1 , wherein the cache memory is to be at the specified memory hierarchy level.

9. The processor of claim 1 , wherein the cache memory is to be at a lower level than the specified memory hierarchy level.

10. A processor comprising:
at least one cache memory; and
a processor core to fetch an instruction of an instruction set of the processor, the instruction having a format that includes a first parameter to indicate a source memory address, a second parameter to indicate a different destination memory address which is different than the source memory address, and a third parameter to specify a memory hierarchy level for the destination memory address, the processor core to perform the instruction to:
perform a first operation to read data from the source memory address into a buffer of the processor without allocating a cache memory line to store the data; and
perform a second operation to allocate a cache memory line at the destination memory address, and to store the data from the buffer of the processor to the allocated cache memory line, wherein the cache memory line is to be allocated in a first cache memory that is to be based at least in part on the memory hierarchy level that is to be specified by the third parameter of the instruction.

11. The processor of claim 10 , wherein the buffer is in a core of the processor.

12. The processor of claim 10 , wherein the buffer comprises a register.

13. The processor of claim 10 , wherein the data is to be read from a main memory into the buffer.

14. The processor of claim 10 , wherein the instruction is to indicate a plurality of source memory addresses.

15. The processor of claim 10 , wherein the first cache memory is to be at the memory hierarchy level.

16. The processor of claim 10 , wherein the first cache memory is to be at a lower level than the memory hierarchy level.

Assignees

• Kim Daehyun
• Kim Changkyu
• Lee Victor W
• Chhugani Jatin
• Satish Nadathur Rajagopalan
• Intel Corp

Inventors

• Kim Daehyun
• Kim Changkyu
• Lee Victor W
• Chhugani Jatin
• Satish Nadathur Rajagopalan

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title