Manufacture method of TFT array substrate and TFT array substrate sturcture

Patent metadata

Field	Value
Publication number	US-9726955-B2
Application number	US-201414430205-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Aug 21, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate ( 1 ), a first metal electrode ( 2 ) on the substrate ( 1 ), a gate isolation layer ( 3 ) positioned on the substrate ( 1 ) and completely covering the first metal electrode ( 2 ), an island shaped semiconductor layer ( 4 ) on the gate isolation layer ( 3 ), a second metal electrode ( 6 ) on the gate isolation layer ( 3 ) and the island shaped semiconductor layer ( 4 ), a protecting layer ( 8 ) on the second metal electrode ( 6 ), a color resist layer ( 7 ) on the protecting layer ( 8 ), a protecting layer ( 12 ) on the color resist layer ( 7 ) and a first pixel electrode layer ( 9 ) on the protecting layer ( 12 ); a via ( 81 ) is formed on the protecting layer ( 8 ), the color resist layer ( 7 ) and the protecting layer ( 12 ), and an organic material layer ( 10 ) fills the inside of the via ( 81 ).

First claim

What is claimed is:

1. A manufacture method of a thin film transistor (TFT) array substrate, comprising steps of:
step 1 , providing a substrate, and deposing and patterning a first metal layer on the substrate to form a first metal electrode;
step 2 , forming a gate isolation layer and an island shaped semiconductor layer on the first metal electrode and the substrate;
step 3 , deposing and patterning a second metal layer on the gate isolation layer and the island shaped semiconductor layer to form a second metal electrode;
step 4 , deposing and patterning a first layer on the second metal electrode for forming a first protecting layer;
step 5 , coating a color resist layer on the first protecting layer, and deposing and patterning a second layer on the color resist layer for forming a second protecting layer, and forming a via in the second protecting layer, the color resist layer and the first protecting layer so as to expose a portion of the second metal electrode; and
step 6 , forming a pixel electrode layer and an organic material layer on the second protecting layer and the second metal electrode, wherein step 6 comprises the following sub-steps:
forming a first pixel electrode layer on the second protecting layer and the portion of the second metal electrode exposed in the via;
coating the organic material layer on the first pixel electrode layer so that the organic material fills up the via;
removing portions of the organic material layer that are located outside and around the via such that a remaining portion of the organic material layer is left in the via and a portion of the first pixel electrode layer that is located outside and around the via is exposed;
forming a second pixel electrode layer on the exposed portion of the first pixel electrode layer that is located outside the via and the remaining portion of the organic material layer that is left in the via; and
patterning the first pixel electrode layer and the second pixel electrode layer at the same time with one photolithography process to form, respectively, a first pixel electrode and a second pixel electrode that collectively form a pixel electrode that is connected to the second metal electrode through the via.

2. The manufacture method of the TFT array substrate according to claim 1 , wherein from the first step to the fourth step, a Physical Vapor Deposition or a Chemical Vapor Deposition is employed for deposing the first metal electrode layer, the gate isolation layer, a semiconductor layer from which the island shaped semiconductor layer was formed, the second metal electrode layer and the first and second protecting layers.

3. The manufacture method of the TFT array substrate according to claim 1 , wherein in the first step, the substrate is a glass substrate; in the second step, the island shaped semiconductor layer is formed with amorphous silicon, and the gate isolation layer and the island shaped semiconductor layer are sequentially formed by processes of film formation, exposure, development and etching.

4. The manufacture method of the TFT array substrate according to claim 1 , wherein in the fifth step, the color resist layer is a red/green/blue color resist layer, and a diameter of a top of the via is 20 μm, and the organic material layer is formed with a photoresist type material.

5. The manufacture method of the TFT array substrate according to claim 1 , wherein the first pixel electrode layer is formed of a material of indium tin oxide (ITO) or indium zinc oxide (IZO) through physical vapor deposition.

6. The manufacture method of the TFT array substrate according to claim 1 , wherein the second pixel electrode layer is formed of a material of indium tin oxide (ITO) or indium zinc oxide (IZO) through physical vapor deposition.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Sun Bo
• Xu Hongyuan
• Hsiao Hsiangchih
• Su Changi
• Zeng Mian
• Wang Xiaoxiao

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title