Systems and methods for automatic test pattern generation for integrated circuit technologies

Patent metadata

Field	Value
Publication number	US-9726722-B1
Application number	US-201414284923-A
Country	US
Kind code	B1
Filing date	May 22, 2014
Priority date	May 24, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Systems and methods are provided for an integrated circuit system. A plurality of separate integrated circuit dies are coupled together to form an integrated circuit package, a first integrated circuit die including an input and a last integrated circuit die including an output, ones of the plurality of integrated circuit dies including a testing circuit associated with a corresponding integrated circuit die. The testing circuit includes a testing path for testing functionality of the corresponding integrated circuit die, a bypass path bypassing the testing path, and control circuitry for selecting between an output of the testing path and an output of the bypass path, the control circuitry being configured to select the output of the testing path or the output of the bypass path and to pass the selected output to a subsequent integrated circuit die among the plurality of coupled circuit dies.

First claim

It is claimed:

1. An integrated circuit system, comprising:
a plurality of separate integrated circuit dies that are coupled together to form an integrated circuit package, a first integrated circuit die including an input and a last integrated circuit die including an output, ones of the plurality of integrated circuit dies comprising:
a testing circuit associated with a corresponding integrated circuit die, the testing circuit including a testing path for testing functionality of the corresponding integrated circuit die, a bypass path bypassing the testing path, and control circuitry for selecting between an output of the testing path and an output of the bypass path, the control circuitry being configured to select the output of the testing path or the output of the bypass path and to pass the selected output to a subsequent integrated circuit die among the plurality of coupled circuit dies, wherein the testing path comprises,
a decompression circuit configured to receive test stimulus data and to generate decompressed stimulus data, and
testing circuitry configured to generate test results data based on scan chain testing of the decompressed stimulus data.

2. The integrated circuit package of claim 1 , wherein the input of the first integrated circuit die is configured to receive test stimulus data from an external testing circuit, and wherein the output of the last integrated circuit die is configured to provide test results data to the external testing circuit.

3. The integrated circuit package of claim 2 , wherein the test stimulus data includes a selector signal that indicates which of the integrated circuit dies among the plurality of coupled integrated circuit dies is to be tested in a current cycle.

4. The integrated circuit package of claim 3 , wherein the corresponding integrated circuit die is configured to select the output of the testing path when the selector signal indicates that the corresponding integrated circuit die is to be tested in the current cycle, and wherein the corresponding integrated circuit die is configured to select the output of the bypass path when the selector signal indicates that the corresponding integrated circuit die is not to be tested in the current cycle.

5. The integrated circuit package of claim 3 , wherein the plurality of integrated circuit dies are identified in a logical order, wherein when the corresponding integrated circuit die is not to be tested in the current cycle, the corresponding integrated circuit die passes test stimulus data or test results data from a prior integrated circuit die to a subsequent integrated circuit die via the bypass path.

6. The integrated circuit package of claim 3 , wherein the control circuitry includes a multiplexer, the multiplexer being configured to select the output of the testing path or the output of the bypass path based on the selector signal.

7. The integrated circuit package of claim 2 , wherein the corresponding integrated circuit die is configured to determine whether the corresponding integrated circuit die is to be tested in the current cycle based on a timing of receipt of the test stimulus data at the corresponding integrated circuit die.

8. The integrated circuit package of claim 2 , wherein the plurality of integrated circuit dies further includes one or more intermediate integrated circuit dies, wherein ones of the intermediate integrated circuit dies are configured not to directly communicate with the external testing circuit.

9. The integrated circuit of package of claim 1 , wherein the bypass path is configured to transmit test stimulus data or test results data received from a preceding integrated circuit die to a succeeding integrated circuit die without modification of the test stimulus data or the test results data.

10. The integrated circuit package of claim 1 , wherein the plurality of integrated circuit dies are mutually coupled through an interposer as part of a 2.5 dimension integrated circuit system, a 3 dimension integrated circuit system, a die tower integrated circuit system, or a multi-chip module (MCM) integrated circuit system.

11. The integrated circuit package of claim 1 , wherein ones of the integrated circuit dies are connected in series.

12. The integrated circuit package of claim 1 , wherein the control circuitry is configured to determine whether the corresponding integrated circuit die is currently being tested and to select the output of the testing path or the output of the bypass path based on the determination of whether the corresponding integrated circuit die is currently being tested.

13. A method of testing a plurality of mutually interconnected integrated circuit dies forming an integrated circuit system, comprising:
receiving test stimulus data at an input of a first integrated circuit die of the plurality of serially connected integrated circuit dies;
determining with control circuitry whether the first integrated circuit die is currently being tested at a testing circuit of the first integrated circuit die based on a selector signal in the test stimulus data or a timing of receipt of the test stimulus data;
in response to determining that the first integrated circuit die is currently being tested, decompressing the test stimulus data with a decompression circuit in a testing path of the testing circuit to generate decompressed stimulus data, generating test results data based on scan chain testing of the decompressed stimulus data, and transmitting the test results data from the testing path of the testing circuit of the first integrated circuit die to a next integrated circuit die among the interconnected circuit dies; and
in response to determining that the first integrated circuit die is not currently being tested, transmitting the test stimulus data from a bypass path of the testing circuit of the first integrated circuit die to the next integrated circuit die, the bypass path bypassing the testing path.

14. The method of claim 13 , further comprising:
receiving data from the first integrated circuit die at the next integrated circuit die, the received data being test results data or test stimulus data;
determining whether the next integrated circuit die is currently being tested at a testing circuit of the next integrated circuit die;
transmitting test results data from a testing path of the testing circuit of the next integrated circuit die when the next integrated circuit die is currently being tested; and
transmitting the received data from the first integrated circuit die from a bypass path of the testing circuit of the next integrated circuit die when the next integrated circuit die is not currently being tested.

15. The method of claim 13 , further comprising:
receiving upstream data from preceding integrated circuit dies at one or more additional integrated circuit dies;
determining whether an additional integrated circuit die is being tested based on selector signal in the upstream data;
outputting bypass data when the additional integrated circuit die is not currently being tested;
outputting test results data generated by the additional integrated circuit die when the additional integrated circuit die is currently being tested.

16. The method of claim 13 , further comprising:
outputting from a last integrated circuit die of the plurality of integrated circuit dies to a testing circuit tests results data for a particular integrated circuit die being tested among the plurality of integrated circuit dies.

Assignees

• Marvell Israel (M I S L) Ltd
• Marvell Israel (M I S L ) Ltd

Inventors

• Solt Yosef

Classifications

• G01R31/31712 Primary

  Input or output aspects · CPC title

• G01R31/318555 Primary

  Control logic · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/3025

  Wireless interface with the DUT · CPC title

• G01R31/318547

  Data generators or compressors · CPC title