Power module substrate, power module substrate with heatsink, power module, and method for producing power module substrate

US9723707B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9723707-B2
Application numberUS-201314388051-A
CountryUS
Kind codeB2
Filing dateMar 29, 2013
Priority dateMar 30, 2012
Publication dateAug 1, 2017
Grant dateAug 1, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A power module substrate includes a circuit layer, an aluminum layer arranged on a surface of an insulation layer, and a copper layer laminated on one side of the aluminum layer. The aluminum layer and the copper layer are bonded together by solid phase diffusion bonding.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power module substrate comprising: a ceramic substrate, and a circuit layer formed on a surface of the ceramic substrate, wherein the circuit layer includes an aluminum layer arranged on the surface of the ceramic substrate and, a copper layer laminated on one side of the aluminum layer by solid phase diffusion bonding, wherein a diffusion layer including Cu and Al is formed in a bonding interface between the aluminum layer and the copper layer, wherein the diffusion layer has a structure in which a plurality of intermetallic compounds is laminated along the bonding interface, wherein each of the plurality of intermetallic compounds is formed in a form of a layer, wherein the plurality of intermetallic compounds includes a θ phase, and an η2 phase, and wherein a layer of each phase is arranged in order of the θ phase and the η2 phase from the aluminum layer toward the copper layer. 2. The power module substrate according to claim 1 , wherein a bonding interface between the copper layer and the diffusion layer has a configuration in which an oxide is dispersed in the form of a layer along the bonding interface. 3. The power module substrate according to claim 1 , wherein a thickness of the copper layer is 0.1 to 6.0 mm. 4. The power module substrate according to claim 1 , wherein the aluminum layer is formed by bonding an aluminum plate having a purity of 99.99% by mass or more to the ceramic substrate. 5. The power module substrate according to claim 1 , wherein a thickness of the diffusion layer is 1 to 80 μm. 6. The power module substrate according to claim 1 , wherein the diffusion layer has a concentration gradient in which the concentration of aluminum atoms lowers gradually and the concentration of copper atoms increases gradually toward the copper layer from the aluminum layer. 7. The power module substrate according to claim 1 , wherein the plurality of intermetallic compounds further includes a ζ2 phase, and a layer of the ζ2 phase is formed between the η2 phase and the copper layer. 8. A power module substrate with a heatsink comprising: the power module substrate according to claim 1 ; and the heatsink bonded to the other side of the power module substrate. 9. The power module substrate with a heatsink according to claim 8 , wherein the bonding layer has a concentration gradient in which a concentration of copper atoms gradually decreases and a concentration of aluminum atoms gradually increases from the aluminum layer toward the heatsink. 10. A power module comprising: the power module substrate according to claim 1 ; and a semiconductor device bonded to the one side of the circuit layer. 11. A method for producing a power module substrate comprising a ceramic substrate and a circuit layer formed on a surface of the ceramic substrate, the method comprises: a circuit layer forming step in which the circuit layer is formed on a surface of the ceramic substrate; wherein the circuit layer forming step comprises: an aluminum layer arranging step in which an aluminum layer is arranged on the surface of the ceramic substrate; and a copper laminating step in which a copper layer is laminated on one side of the aluminum layer after the aluminum layer arranging step, wherein in the copper laminating step, the aluminum layer and the copper layer are bonded together by solid phase diffusion bonding, and a diffusion layer including Cu and Al is formed in a bonding interface between the aluminum layer and the copper layer, wherein the diffusion layer has a structure in which a plurality of intermetallic compounds is laminated along the bonding interface, wherein each of the plurality of intermetallic compounds is formed in a form of a layer, wherein the plurality of intermetallic compounds includes a θ phase, and an η2 phase, and wherein a layer of each phase is arranged in order of the θ phase and the η2 phase from the aluminum layer toward the copper layer. 12. The method for producing a power module substrate according to claim 11 , wherein in the copper laminating step, the copper layer is laminated on one side of the aluminum layer, and the aluminum layer and the copper layer are bonded together by solid phase diffusion bonding by maintaining at 400° C. or more to less than 548° C. in a state of pressurizing the aluminum layer and the copper layer at a pressure of 3 to 35 kgf/cm 2 .

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • comprising metals or metalloids, e.g. solders · CPC title

  • of die-attach connectors · CPC title

  • by flowing liquids, e.g. forced water cooling · CPC title

  • H10W40/255Primary

    having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

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Frequently asked questions

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What does patent US9723707B2 cover?
A power module substrate includes a circuit layer, an aluminum layer arranged on a surface of an insulation layer, and a copper layer laminated on one side of the aluminum layer. The aluminum layer and the copper layer are bonded together by solid phase diffusion bonding.
Who is the assignee on this patent?
Mitsubishi Materials Corp
What technology area does this patent fall under?
Primary CPC classification H10W40/255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).