Clock domain bridge static timing analysis

Patent metadata

Field	Value
Publication number	US-9722767-B2
Application number	US-201514749905-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Examples for performing static timing analysis on clocked circuits are described. An example static timing analysis computing device includes a logic device, and a storage device holding instructions executable by the logic device, the instructions including instructions executable to receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock, receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit, apply the constraint in a static timing analysis of the signal path in the cross-domain circuit, and output a result based upon applying the static timing analysis constraint.

First claim

The invention claimed is:

1. A computing device, comprising:
a logic device; and
a storage device holding instructions executable by the logic device to
receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock;
receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit;
apply the statistic timing analysis constraint to be met by the signal traveling the signal path in the cross-domain circuit by determining a result of:
DataTravel≦ i*T RCYC −t SU −t H −R ClkSkew, or  (1)

( DCR+CQR+DDR )−( DCG+CQG+DDG )≦2* T RCYC −t SU −t H −( DCS−DCD ),  (2)

wherein, in (1) and (2), DataTravel includes a difference between travel time of a change in data propagating from the first clock to a capture register and travel time from the first clock to a first synchronization flip-flop circuit of one or more synchronization flip-flop circuits in the cross-domain circuit, RClkSkew includes a difference in clock insertion delay between the second clock and the first synchronization flip-flop circuit and the second clock and the capture register, i represents a number of synchronization flip-flops through which the signal passes, DCR includes a clock insertion delay to a register file, CQR includes a clock-to-output delay of all flip-flop circuits in the register file, DDR includes a routing delay from the register file to the capture register, DCG includes a clock insertion delay to a gray code counter, CQG includes a clock-to-output delay of the gray code counter, DDG includes a routing delay from the gray code counter to the first synchronization flip-flop circuit of the one or more synchronization flip-flop circuits, DCD includes a clock insertion delay to flip-flop circuits in the capture register, DCS includes a clock insertion delay to the first synchronization flip-flop circuit, T RCYC includes a cycle time of the second clock, t SU includes a flip-flop setup time of the flip-flop circuits in the capture register, and t H includes a flip-flop hold time of the first synchronization flip-flop circuit; and
output a result based upon applying the static timing analysis constraint.

2. The computing device of claim 1 , wherein the signal path is a first signal path and is a control signal path configured to control data sampling at a destination register, and the static timing analysis constraint is further based upon one or more delays in a second signal path configured to deliver data to the destination register.

3. The computing device of claim 1 , wherein the signal path is a first gray code bit synchronization path for a first gray code pointer bit for a gray code buffer index, wherein the static timing analysis constraint is based upon one or more delays in a second gray code bit synchronization path for a second gray code pointer bit for the gray code buffer index, wherein each of the first gray code pointer bit and the second gray code pointer bit is generated by the gray code counter, the gray code counter comprising a flip-flop circuit for each gray code pointer bit, and wherein an output of the gray code buffer index is provided to the capture register.

4. The computing device of claim 1 , wherein the cross-domain circuit is an asynchronous FIFO circuit, wherein the signal path is a round trip synchronization path of a write pointer in the asynchronous FIFO circuit from a write clock input at a write-side address counter to an address subtractor at a read-side of the cross-domain circuit, and from a read clock input at a read-side address counter to an address subtractor at a write-side of the asynchronous FIFO circuit.

5. The computing device of claim 1 , wherein the static timing analysis constraint is further determined based upon measurements of delays that occur during a momentary phase alignment between the first clock and the second clock.

6. The computing device of claim 2 , wherein the first signal path includes a toggle flip-flop circuit that provides a control signal to one or more synchronization flip-flop circuits and the second signal path includes a synchronization register that delivers the data to the destination register.

7. The computing device of claim 3 , wherein applying the static timing analysis constraint includes determining a result of
SignalSkew MN≦T WCYC −t SUM −t HN −R CLKSkew NM,   (6)

SignalSkew MN≦T RCYC −t SUM −t HN −W CLKSkew NM,   (7)

( DWM+CQM+DM )−( DWN+CQN+DN )≦ T WCYC −t SUM −t HN −( DRN−DRM ), or  (8)

( DWM+CQM+DM )−( DWN+CQN+DN )≦ T RCYC −t SUM −t HN −( DRN−DRM ),  (9)

where, in (6), (7), (8), and (9), SignalSkewMN includes the difference between sums of clock insertion delays, clock-to-output delays, and routing delays for gray code pointer bits M and N, T WCYC includes a minimum cycle time of a write clock controlling timing of the write pointer gray-code counter, RCLKSkewNM includes a difference between clock insertion delays to synchronizer flip-flop circuits for the write pointer gray-code counter bits M and N, WCLKSkewNM includes a difference between clock insertion delays to synchronizer flip-flop circuits for the read pointer gray-code counter bits M and N, DWM includes a clock insertion delay to the flip-flop circuit for the first gray-code counter bit, CQM includes a clock-to-output delay of the flip-flop circuit for the first gray-code counter bit, DM includes a routing delay from the flip-flop circuit for the first gray-code counter bit to a first synchronization flip-flop for that bit, DWN includes a clock insertion delay to the flip-flop circuit for the second gray-code counter bit, CQN includes a clock-to-output delay of the flip-flop circuit for the second gray code counter bit, DN includes a routing delay from the flip-flop circuit for the second gray-code counter bit to the synchronization flip-flop for that bit, T RCYC includes a minimum cycle time of a read clock controlling timing of the read pointer gray-code counter, t SUM includes a flip-flop setup time of the flip-flop circuit in the synchronization flip-flop of the first bit, t HN includes a flip-flop hold time of the synchronization flip-flop of the second bit, DRN includes a clock insertion delay to the synchronization flip-flop of the second bit, and DRM includes a clock insertion delay to the synchronization flip-flop of the first bit.

8. The computing device of claim 4 , wherein applying the static timing analysis constraint further includes determining a result of
( DCG+CQG+DDG+t SUW )− DCT +( DCA+CQA+DDA+t SUR )− DCS≦T XCYC +3* TΔ,   (10)

( DCG+CQG+DDG+t SUW )− DCT +( DCA+CQA+DDA+t SUR )− DCS≦J*T CYC , or  (11)

( DCG+CQG+DDG+t SUW )− DCT +( DCA+CQA+DDA+t SUR )− DCS≦T CYC ,  (12)

where, in (10), (11), and (12), T Δ =|T WCYC −T RCYC |, T XCYC =max(T WCYC ,T RCYC ),
J=K−5 for “K” FIFO levels, DCG includes a clock insertion delay to the write pointer, CQG includes a clock-to-output delay of the write pointer, DDG includes a routing delay from the write pointer to a first synchronization flip-flop circuit in the wclk to rclk synchronization chain, t SUW includes a flip-flop setup time of the first synchronization flip-flop, DCT includes a clock insertion delay to a first synchronization flip-flop circuit in the rclk to wclk synchronization chain, DCA includes a clock insertion delay to the read pointer, CQA includes a clock-to-output delay of the read pointer, DDA includes a routing delay from the read pointer to the first syn

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Simpson Miles

Classifications

• H04L7/005

  Correction by an elastic buffer · CPC title

• G06F5/06 Primary

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H04L7/0012

  by comparing receiver clock with transmitter clock · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title