Semiconductor device comprising successive approximation register analog to digital converter with variable sampling capacitor

Patent metadata

Field	Value
Publication number	US-9722624-B2
Application number	US-201615074447-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Apr 20, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A semiconductor device and operating method thereof are provided. The semiconductor device includes a mode controller configured to output a control signal of a first level in a first mode, and output a control signal of a second level that is different from the first level in a second mode that is different from the first mode; and a successive approximation register analog-to-digital converter (SAR ADC) configured to convert an analog input signal into a digital output signal using a plurality of variable sampling capacitors, wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance, wherein, in the first mode, the SAR ADC is configured to receive the control signal of the first level and connect the first sampling capacitor and the second sampling capacitor to either of a first voltage and a second voltage that is different from the first voltage to convert the analog input signal into the digital output signal, and wherein, in the second mode, the SAR ADC is configured to receive the control signal of the second level and connect any one of the first sampling capacitor and the second sampling capacitor to either of the first voltage and the second voltage to convert the analog input signal into the digital output signal.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a mode controller configured to output a control signal that has a first level in a first mode or a second level in a second mode, the first mode being different from the second mode, the first level being different from the second level; and
a successive approximation register analog-to-digital converter (SAR ADC) configured to convert an analog input signal into a digital output signal using a plurality of variable sampling capacitors,
wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance,
wherein, in the first mode, the SAR ADC is configured to receive the control signal having the first level from the mode controller, connect a first end of the second sampling capacitor to either of a first voltage and a second voltage that is different from the first voltage to convert the analog input signal into the digital output signal and switchably connect second ends of the first sampling capacitor and the second sampling capacitor to the analog input signal, and
wherein, in the second mode, the SAR ADC is configured to receive the control signal having the second level from the mode controller, disconnect the first end of the second sampling capacitor from either of the first voltage and the second voltage to convert the analog input signal into the digital output signal and switchably connect the second ends of the first sampling capacitor and the second sampling capacitor to the analog input signal.

2. The semiconductor device of claim 1 , wherein the first capacitance of the first sampling capacitor is equal to the second capacitance of the second sampling capacitor.

3. The semiconductor device of claim 1 , wherein the analog input signal has a first frequency in the first mode and
has a second frequency in the second mode that is greater than the first frequency.

4. The semiconductor device of claim 1 , wherein the plurality of variable sampling capacitors further comprises a plurality of first variable sampling capacitors, a bridge capacitor, and a plurality of second variable sampling capacitors,
wherein the plurality of first variable sampling capacitors has a binary-weighted structure, and
wherein the plurality of second variable sampling capacitors has a thermometer code structure.

5. The semiconductor device of claim 1 , further comprising:
a first interlayer insulating film in which the first sampling capacitor is formed; and
a second interlayer insulating film in which the second sampling capacitor is formed,
wherein the second interlayer insulating film is disposed on the first interlayer insulating film.

6. The semiconductor device of claim 1 , wherein the first capacitance is greater than the second capacitance.

7. The semiconductor device of claim 1 , further comprising:
a decimation filter configured to filter the digital output signal in the first mode.

8. The semiconductor device of claim 1 , wherein the plurality of variable sampling capacitors further comprises a plurality of first variable sampling capacitors, a bridge capacitor, and a plurality of second variable sampling capacitors, and
wherein the plurality of first variable sampling capacitors and the plurality of second variable sampling capacitors each has any one of a binary-weighted structure and a thermometer code structure.

9. The semiconductor device of claim 1 , wherein the plurality of variable sampling capacitors has any one of a binary-weighted capacitor structure and a thermometer code structure.

10. A semiconductor device, comprising:
a comparator having an input node;
a successive approximation register (SAR) controller is configured to convert a first analog input signal into a first digital output signal under control of a control signal having a first level, by adjusting a voltage of the input node using a first sampling capacitor if an analog input signal is the first analog input signal, and convert a second analog input signal that is different from the first analog input signal into a second digital output signal under control of the control signal having a second level, the second level being different from the first level, by adjusting the voltage of the input node using a second sampling capacitor having a capacitance that is less than a capacitance of the first sampling capacitor if the analog input signal is the second analog input signal, wherein the analog input signal is switchably connected to the input node; and
a decimation filter configured to filter the first digital output signal and not filter the second digital output signal.

11. The semiconductor device of claim 10 , wherein the first analog input signal has a first frequency, and
the second analog input signal has a second frequency that is greater than the first frequency.

12. The semiconductor device of claim 11 , wherein the first sampling capacitor comprises a plurality of first sampling capacitors that has 2nC as a capacitance value, wherein n is a natural number a C is a rational number, and
the second sampling capacitor comprises a plurality of second sampling capacitors that has nC as a capacitance value.

13. The semiconductor device of claim 12 , wherein the SAR controller is configured to connect each of the plurality of first sampling capacitors to any one of a first voltage and a second voltage that is different from the first voltage, if the first analog input signal is converted into the first digital output signal, and
connect each of the plurality of second sampling capacitors to any one of the first voltage and the second voltage, if the second analog input signal is converted into the second digital output signal.

14. The semiconductor device of claim 12 , wherein the plurality of first sampling capacitors comprises a plurality of third sampling capacitors, a bridge capacitor, and a plurality of fourth sampling capacitors,
wherein the third sampling capacitors have a binary-weighted structure, and
wherein the fourth sampling capacitors have a thermometer code structure.

15. A semiconductor device, comprising:
a plurality of variable sampling capacitors, wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance;
a comparator having a first input node connected to the plurality of variable sampling capacitors and a second input node connected to a comparison voltage;
a successive approximation register (SAR) controller configured to receive an output of the comparator, and connect each of the plurality of variable sampling capacitors to one of a first voltage and a second voltage that is different from the first voltage;
a decimation filter connected to the SAR controller; and
an output unit configured to output any one of an output of the decimation filter and an output of the SAR controller depending on a control signal.

16. The semiconductor device of claim 15 , wherein the output unit comprises a multiplexer configured to output the output of the decimation filter if the control signal of a first level is applied, and output the output of the SAR controller if the control signal of a second that is level different from the first level is applied.

17. The semiconductor device of claim 15 , wherein each of the plurality of variable sampling capacitors further comprises:
a first switching element configured to be controlled by a switching signal output

Assignees

• Lee Jong-Woo
• Oh Seung-Hyun
• Cho Thomas Byung-Hak
• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Woo
• Oh Seung-Hyun
• Cho Thomas Byung-Hak

Classifications

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/442 Primary

  using switched capacitors · CPC title