Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

Patent metadata

Field	Value
Publication number	US-9721922-B2
Application number	US-201314139614-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a conductive layer over the substrate;
disposing a semiconductor die over the conductive layer;
disposing a first encapsulant over the semiconductor die, substrate, and conductive layer;
removing a portion of the substrate to expose the conductive layer after depositing the first encapsulant;
disposing a second encapsulant around the first encapsulant and conductive layer after removing the portion of the substrate; and
forming an interconnect structure over the conductive layer and second encapsulant.

2. The method of claim 1 , further including disposing a first passive device over the conductive layer.

3. The method of claim 2 , further including disposing a second passive device adjacent to the conductive layer.

4. The method of claim 1 , further including:
providing the substrate to include an insulating layer;
forming the conductive layer over the insulating layer; and
forming a plurality of openings in the insulating layer over the conductive layer.

5. The method of claim 4 , further including removing the portion of the substrate prior to forming the openings in the insulating layer.

6. The method of claim 1 , further including disposing an interconnect unit including a conductive via in a peripheral region of the semiconductor die.

7. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
disposing a first semiconductor die over the first conductive layer;
disposing a second semiconductor die over the first conductive layer adjacent to the first semiconductor die;
disposing a first encapsulant over the first semiconductor die, second semiconductor die, and first conductive layer;
singulating through the first encapsulant with the first semiconductor die remaining attached to the second semiconductor die by the first encapsulant;
removing a portion of the substrate over the first conductive layer;
depositing a second encapsulant over the first semiconductor die, second semiconductor die, first conductive layer, and first encapsulant after singulating through the first encapsulant; and
forming an interconnect structure over the first conductive layer opposite the first semiconductor die.

8. The method of claim 7 , wherein forming the interconnect structure includes forming a second conductive layer over the first encapsulant and first conductive layer by performing a metal deposition technique onto the first conductive layer.

9. The method of claim 7 , further including disposing a passive device in a peripheral region of the first semiconductor die.

10. The method of claim 9 , further including depositing the second encapsulant over the passive device and first semiconductor die.

11. The method of claim 7 , further including:
disposing vertical interconnect structure in a peripheral region of the first semiconductor die;
depositing the first encapsulant around the first semiconductor die and vertical interconnect structure; and
forming an opening in the first encapsulant over the vertical interconnect structure.

12. The method of claim 7 , further including forming a composite interconnect structure over the first semiconductor die.

13. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first interconnect structure over the substrate;
disposing a first semiconductor die over the first interconnect structure;
disposing a second encapsulant over the first semiconductor die and first interconnect structure;
singulating through the second encapsulant;
disposing a first encapsulant over the first semiconductor die and first interconnect structure after singulating through the second encapsulant;
removing a portion of the substrate over the first interconnect structure; and
forming a second interconnect structure over the first encapsulant and first interconnect structure.

14. The method of claim 13 , further including disposing a passive device over the first interconnect structure.

15. The method of claim 13 , further including disposing a passive device adjacent to the first interconnect structure.

16. The method of claim 13 , further including disposing a vertical interconnect structure in a peripheral region of the first semiconductor die.

17. The method of claim 16 , further including forming an opening in the first encapsulant over the vertical interconnect structure.

18. The method of claim 13 , further including disposing a second semiconductor die over the first interconnect structure.

19. A method of making a semiconductor device, comprising:
providing a substrate including an insulating layer and a conductive layer;
forming a first interconnect structure over the substrate and connected to the conductive layer;
disposing a semiconductor die over the first interconnect structure;
disposing a first encapsulant over the substrate, first interconnect structure, and semiconductor die; and
removing a portion of the insulating layer after forming the first interconnect structure to expose the conductive layer.

20. The method of claim 19 , further including disposing a second encapsulant around the substrate, semiconductor die, first interconnect structure, and first encapsulant.

21. The method of claim 19 , further including disposing a vertical interconnect structure in a peripheral region of the semiconductor die.

22. The method of claim 20 , further including forming a second interconnect structure over the second encapsulant outside a footprint of the first encapsulant.

23. The method of claim 20 , further including singulating through the first encapsulant prior to depositing the second encapsulant.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Marimuthu Pandi C
• Lin Yaojian
• Choi Won Kyoung
• Shim Il Kwon

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title