Land side and die side cavities to reduce package z-height

Patent metadata

Field	Value
Publication number	US-9721882-B2
Application number	US-201715419087-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Sep 28, 2012
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

First claim

What is claimed:

1. An apparatus, comprising:
a package substrate, the package substrate having a die side, and a land side opposite the die side, the package substrate having a plurality of buildup layers;
a die coupled to the package substrate;
a cavity on a land side of the buildup layers; and
a capacitor mounted in the cavity, wherein the capacitor protrudes from the land side of the substrate by a distance less than or equal to a land side solder bump thickness.

2. The apparatus of claim 1 , wherein the cavity is within an outermost layer of the plurality of buildup layers.

3. The apparatus of claim 1 , wherein e cavity is within more than one layer of the plurality of buildup layers.

4. The apparatus of claim 1 , wherein the plurality of buildup layers includes one or more organic dielectric layers.

5. The apparatus of claim 1 , further including a PCB having a first side and a second side, wherein the land side of the package substrate is mounted to the PCB with a space between the capacitor and the PCB.

6. The apparatus of claim 5 , further including a second package substrate coupled to the second side of the PCB.

7. The apparatus of claim 5 , wherein a footprint of the package substrate is at least partially aligned over a footprint of the second package substrate.

8. A computing device, comprising:
a PCB, having a first side and a second side;
a package substrate having a plurality of buildup layers, the package substrate mounted to the first side of the PCB on a land side of the package substrate;
a die mounted to a die side of the package substrate;
a cavity in an outermost layer of the land side of the buildup layers;
a capacitor mounted within the cavity, wherein the capacitor protrudes from package substrate by a distance less than or equal to a land side solder bump thickness; and
an antenna coupled to the PCB.

9. The computing device of claim 8 , further including a touchscreen display.

10. The computing device of claim 9 , further including a battery.

11. The computing device of claim 10 , wherein the computing device is a mobile phone.

12. The computing device of claim 8 , wherein the plurality of buildup layers is four buildup layers.

13. The computing device of claim 12 , wherein the plurality f buildup layers includes one or more organic dielectric layers.

14. The computing device of claim 8 , further including a second package substrate coupled to the second side of the PCB.

15. An apparatus, comprising:
a package substrate, the package substrate having a die side, and a land side opposite the die side, the package substrate having a plurality of buildup layers;
a die coupled to the package substrate;
a cavity on a land side of the buildup layers; and
a capacitor mounted in the cavity, wherein the capacitor protrudes from the land side of the substrate by a distance less than or equal to a thickness of a solder bump to be formed on the land side of the substrate.

16. The apparatus of claim 15 , wherein the cavity is within an outermost layer of the plurality of buildup layers.

17. The apparatus of claim 15 , wherein the cavity is within more than one layer of the plurality of buildup layers.

18. The apparatus of claim 15 , wherein the plurality of buildup layers includes one or more organic dielectric layers.

19. The apparatus of claim 15 , further including a PCB having a first side and a second side, wherein the land side of the package substrate is mounted to the PCB with a space between the capacitor and the PCB.

20. The apparatus of claim 19 , further including a second package substrate coupled to the second side of the PCB.

Assignees

• Intel Corp

Inventors

• Hossain Md Altaf
• Gilbert Scott A

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title