High-k / metal gate CMOS transistors with TiN gates

Patent metadata

Field	Value
Publication number	US-9721847-B2
Application number	US-201514724185-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Dec 31, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising the steps of:
forming a thick TiN layer in both a PMOS transistor area and an NMOS transistor area;
annealing the thick TiN layer in oxygen;
after annealing, removing the thick TiN layer in the NMOS transistor area; and
after removing the thick TiN layer in the NMOS transistor area, forming a thin TiN layer in both the PMOS transistor area and in the NMOS transistor area, the thin TiN layer being thinner than the thick TiN layer and having a reduced oxygen concentration.

2. The process of claim 1 , wherein the thick TiN metal gate material has a thickness greater than 8 nm and where the thin TiN metal has a thickness between 1 to 3 nm.

3. The process of claim 1 , wherein the thick TiN metal gate material has a thickness of 10 nm and where the thin TiN metal has a thickness of 2 nm.

4. The process of claim 1 , wherein the PMOS transistor is a gate first metal gate PMOS transistor and where the NMOS transistor is a gate first metal gate transistor further comprising the steps of:
depositing doped polysilicon on the thin TiN layer;
forming a transistor gate pattern on the doped polysilicon with a PMOS transistor gate pattern and with an NMOS transistor gate pattern;
etching the doped polysilicon and the thin TiN layer and the thick TiN layer to form a gate of the PMOS transistor; and
etching the polysilicon and the thin TiN layer to form a gate of the NMOS transistor.

5. The process of claim 1 , wherein the PMOS transistor is a replacement metal gate PMOS transistor and where the NMOS transistor is a replacement metal NMOS transistor further comprising the steps of:
prior to the step of forming the thick TiN layer;
removing a polysilicon gate from an NMOS replacement gate transistor to form an NMOS replacement gate transistor trench in the NMOS transistor area; and
removing a polysilicon gate from a PMOS replacement gate transistor to form a PMOS replacement gate transistor trench in the PMOS transistor area.

6. The process of claim 1 , wherein the PMOS transistor is a high-k last, gate first metal gate PMOS transistor and where the NMOS transistor is a high-k last, gate first metal gate transistor further comprising the steps of:
prior to the step of forming the thick TiN layer, depositing a first high-k dielectric in both the PMOS transistor area and in the NMOS transistor area;
prior to the step of forming the thin TiN layer removing the first high-k dielectric from the NMOS transistor area and depositing a second high-k dielectric in the NMOS transistor area and in the PMOS transistor area;
after the step of forming the thin TiN layer, removing the thin TiN layer from the PMOS transistor area and removing the second high-k dielectric from the PMOS transistor area;
depositing doped polysilicon in the PMOS transistor area and in the NMOS transistor area;
forming a transistor gate pattern on the doped polysilicon with a PMOS transistor gate pattern and with an NMOS transistor gate pattern;
etching the polysilicon and the thick TiN layer to form a gate of the PMOS transistor; and
etching the polysilicon and the thin TiN layer to form a gate of the NMOS transistor.

7. The process of claim 6 , wherein the first and second high-k dielectrics are 1.2 nm HfO x , where the thick TiN has a thickness of 10 nm thick and where the thin TiN has a thickness of 2 nm.

8. The process of claim 1 , wherein the PMOS transistor is a high-k last replacement metal gate PMOS transistor and where the NMOS transistor is a high-k last replacement metal NMOS transistor further comprising the steps of:
prior to the step of forming the thick TiN layer;
removing a polysilicon gate from an NMOS replacement gate transistor to form an NMOS replacement gate transistor trench in the NMOS transistor area;
removing a polysilicon gate from a PMOS replacement gate transistor to form a PMOS replacement gate transistor trench in the PMOS transistor area;
depositing a first high-k dielectric in the PMOS replacement gate transistor trench and in the NMOS transistor area;
prior to the step of forming the thin TiN layer removing the first high-k dielectric from the NMOS transistor area and depositing a second high-k dielectric on the PMOS transistor area and in the NMOS replacement gate transistor trench;
after the step of forming the thin TiN layer;
removing the thin TiN layer from the PMOS transistor area; and
removing the second high-k dielectric from the PMOS transistor area.

9. The process of claim 8 , wherein the first and second high-k dielectrics are 1.2 nm HfO x , where the thick TiN has a thickness of 10 nm and where the thin TiN has a thickness of 2 nm.

10. A process of forming an integrated circuit with replacement metal gate CMOS transistors, comprising the steps:
providing a partially processed integrated circuit with a PMOS transistor with a first polysilicon gate on a first gate dielectric and an NMOS transistor with a second polysilicon gate on a second gate dielectric and with premetal dielectric that overlies the NMOS and PMOS transistors and wherein the premetal dielectric is planarized exposing the top surface of the first and second polysilicon gates;
etching to remove the first and second polysilicon gates from first and second gate dielectric to form a PMOS and an NMOS replacement gate transistor trench;
depositing a first high-k dielectric in the PMOS replacement gate transistor trench;
depositing at least 8 nm of PMOS TiN metal gate material on the first high-k dielectric in the PMOS replacement gate transistor trench and on a second high-k dielectric in the NMOS replacement gate trench;
annealing the PMOS metal gate material in oxygen;
forming an NMOS metal gate pattern with an opening over the NMOS replacement gate transistor trench;
etching the PMOS metal gate material from the NMOS replacement gate transistor trench to remove it from an underlying dielectric;
removing the NMOS metal gate pattern;
depositing second high-k dielectic in the NMOS replacement gate transistor trench;
depositing between about 1 nm and 3 nm NMOS TiN metal gate material with a reduced oxygen concentration on the second high-k dielectric;
depositing a filler metal over the NMOS TiN metal gate material to overfill the PMOS replacement gate transistor trench and to overfill the NMOS replacement gate transistor trench; and
polishing to remove the overfill, and portions of the PMOS TiN metal gate material and the NMOS TiN metal gate material from the surface of the premetal dielectric.

11. The process of claim 10 , wherein the process is a high-k last process and where the underlying dielectric is the second gate dielectric and further comprising:
prior the step of depositing the first high-k dielectric
forming a first PMOS transistor photo resist pattern with an opening over the PMOS replacement gate transistor trench;
etching the first gate dielectric from the PMOS replacement gate transistor trench; and
after the etching the first gate dielectric step, stripping the first PMOS transistor photo resist pattern;

prior to the step of depositing second high-k dielectric etching the second gate dielectric from the NMOS replacement gate transistor trench;
prior to the step of depositing the filler metal; forming a second PMOS transistor photo resist pattern on the integrated circuit with an opening over the PMOS replacement gate transistor trench;
etching the NMOS TiN metal gate material;
etching the NMOS high-k dielectric; and
removing the second PMOS transistor photo resist pattern prior the step of depositing the filler metal.

12. The process of claim 10 , wherein the process is a

Assignees

• Texas Instruments Inc

Inventors

• Niimi Hiroaki
• Kirkpatrick Brian K

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/262

  by physical means only · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title