Non-volatile memory devices, operating methods thereof and memory systems including the same

Patent metadata

Field	Value
Publication number	US-9330770-B2
Application number	US-201514590665-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Feb 17, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

First claim

What is claimed is:

1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
erasing the plurality of serially-connected nonvolatile memory cells by applying a plurality of word line erase voltages to the plurality of serially-connected nonvolatile memory cells via a plurality of word lines, the plurality of word lines being connected to the plurality of serially-connected nonvolatile memory cells respectively; and
verifying the plurality of serially-connected nonvolatile memory cells,
wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate, and
a level of each of the plurality of word line erase voltages is related with a distance between a corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate.

2. The method of claim 1 , wherein the level of each of the plurality of word line erase voltages is lower as the distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater.

3. The method of claim 1 , wherein
the plurality of memory cell strings include a second memory cell string connected to the plurality of word lines,
the first memory cell string and the second memory cell string are connected to a first bit line,
the first memory cell string includes a first ground select transistor,
the second memory cell string includes a second ground select transistor, and
the first ground select transistor and the second ground select transistor are connected a first ground select line.

4. The method of claim 1 , wherein
the plurality of serially-connected nonvolatile memory cells are divided into a plurality of groups,
each of the plurality of groups includes a first memory cell and a second memory cell, and
a level of a first word line erase voltage among the plurality of word line erase voltages that is applied to the first memory cell of each of the plurality of groups is equal to a level of a second word line erase voltage among the plurality of word line erase voltages that is applied to the second memory cell of the same group.

5. The method of claim 4 , wherein the plurality of groups include a first group and a second group,
a distance between the first memory cell included in the first group and the substrate is greater than a distance between the first memory cell included in the second group and the substrate, and
the level of the first word line erase voltage that is applied to the first memory cell included in the first group is higher than the level of the first word line erase voltage that is applied to the first memory cell included in the second group.

6. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
erasing a first memory cell among the plurality of serially-connected nonvolatile memory cells by applying a first word line erase voltage to a first word line connected to the first memory cell; and
erasing a second memory cell among the plurality of serially-connected nonvolatile memory cells by applying a second word line erase voltage to a second word line connected to the second memory cell, a level of the first word line erase voltage being lower than a level of the second word line erase voltage,
wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate, and
a distance between the first memory cell and the substrate is greater than a distance between the second memory cell and the substrate.

7. The method of claim 6 , further comprising:
erasing a third memory cell among the plurality of serially-connected nonvolatile memory cells by applying a third word line erase voltage to a third word line connected to the third memory cell, a level of the third word line erase voltage being lower than the level of the second word line erase voltage, wherein
a distance between the third memory cell and the substrate is greater than the distance between the second memory cell and the substrate.

8. The method of claim 6 , wherein
the plurality of memory cell strings include a second memory cell string connected to the plurality of word lines,
the first memory cell string and the second memory cell string are connected to a first bit line,
the first memory cell string includes a first ground select transistor,
the second memory cell string includes a second ground select transistor, and
the first ground select transistor and the second ground select transistor are connected a first ground select line.

9. The method of claim 6 , further comprising:
erasing a third memory cell adjacent to the first memory cell among the plurality of serially-connected nonvolatile memory cells by applying the first word line erase voltage to a third word line connected to the third memory cell; and
erasing a fourth memory cell adjacent to the second memory cell among the plurality of serially-connected nonvolatile memory cells by applying the second word line erase voltage to a fourth word line connected to the fourth memory cell.

10. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a plurality of serially-connected nonvolatile memory cells, the method comprising:
erasing the plurality of serially-connected nonvolatile memory cells by applying a plurality of word line erase voltages to the plurality of serially-connected nonvolatile memory cells via a plurality of word lines, the plurality of word lines being connected to the plurality of serially-connected nonvolatile memory cells respectively; and
verifying each of the plurality of serially-connected nonvolatile memory cells,
wherein the plurality of serially-connected nonvolatile memory cells are stacked on or above a substrate in a direction that is vertical to the substrate,
the first memory cell string includes a channel hole having diameters corresponding to the plurality of serially-connected nonvolatile memory cells, the diameters being varied according to distances between the substrate and the plurality of serially-connected nonvolatile memory cells,
each of the plurality of word line erase voltages is applied to a corresponding one of the plurality of serially-connected nonvolatile memory cells, and
a level of each of the plurality of word line erase voltages is related with a diameter, among the diameters, of the corresponding one of the plurality of serially-connected nonvolatile memory cells.

11. The method of claim 10 , wherein the level of each of the plurality of word line erase voltages is lower as the diameter of the corresponding one of the plurality of serially-connected nonvolatile memory cells become greater.

12. The method of claim 11 , wherein the diameter of the corresponding one of the plurality of serially-connected nonvolatile memory cells is greater as a distance between the corresponding one of the plurality of serially-connected nonvolatile memory cells and the substrate becomes greater.

13. The method of claim 10 , wherein
the plurality of memory cell strings include a second memory cell string connected to the plural

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shim Sunil
• Jang Jaehoon
• Chae Donghyuk
• Lim Youngho
• Kim Hansoo
• Jeong Jaehun

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• H01L27/11582

  Electricity · mapped topic

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title