Architecture to improve write-ability in SRAM

Patent metadata

Field	Value
Publication number	US-9721650-B1
Application number	US-201615269620-A
Country	US
Kind code	B1
Filing date	Sep 19, 2016
Priority date	Sep 19, 2016
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

First claim

What is claimed is:

1. A memory, comprising:
a memory core having a plurality of memory cells;
a first write assist circuit including write and boost logic, the first write assist configured to assist writing to a first group of the plurality of memory cells of the memory core; and
a second write assist circuit including write and boost logic, the second write assist configured to assist writing to a second group of the plurality of memory cells of the memory core,
wherein the first write assist circuit and the second write assist circuit are located on opposite sides of the memory core and wherein the first write assist circuit and the second write assist circuit are operatively coupled to a bitline, the first write assist circuit configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the first group and the second write assist circuit configured to boost voltage applied to the bitline to write to the one of the plurality of memory cells from the second group.

2. The memory of claim 1 , wherein a first edge cell is between the first write assist circuit and the memory core and a second edge cell is between the second write assist circuit and the memory core.

3. The memory of claim 1 , wherein one or more of the memory cells from the first group and one or more of the memory cells from the second group are arranged in a column.

4. The memory of claim 3 , further comprising a bitline operatively coupled to each of the memory cells in the column.

5. The memory of claim 1 , wherein the first write assist circuit comprises a first boost capacitor configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the first group and the second write assist circuit comprises a second boost capacitor configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the second group.

6. The memory of claim 1 , further comprising a row decoder configured to activate one of the memory cells in the column and enable one of the first and second write assist circuits to assist writing to the activated one of the memory cells.

7. An apparatus, comprising:
at least one processor;
a memory array including:
a memory core having a plurality of memory cells;
a first write assist circuit including write and boost logic, the first write assist configured to assist writing to a first group of the plurality of memory cells of the memory core; and
a second write assist circuit including write and boost logic, the second write assist configured to assist writing to a second group of the plurality of memory cells of the memory core,
wherein the first write assist circuit and the second write assist circuit are located on opposite sides of the memory core and wherein the first write assist circuit and the second write assist circuit are operatively coupled to a bitline, the first write assist circuit configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the first group and the second write assist circuit configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the second group.

8. The apparatus of claim 7 , wherein a first edge cell is between the first write assist circuit and the memory core and a second edge cell is between the second write assist circuit and the memory core.

9. The apparatus of claim 7 , wherein one or more of the memory cells from the first group and one or more of the memory cells from the second group are arranged in a column.

10. The apparatus of claim 9 , further comprising a bitline operatively coupled to each of the memory cells in the column.

11. The apparatus of claim 7 , wherein the first write assist circuit comprises a first boost capacitor configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the first group and the second write assist circuit comprises a second boost capacitor configured to boost voltage applied to the bitline to write to one of the plurality of memory cells from the second group.

12. The apparatus of claim 7 , further comprising a row decoder configured to activate one of the memory cells in the column and enable one of the first and second write assist circuits to assist writing to the activated one of the memory cells.

13. An apparatus, comprising:
a memory array having a plurality of memory cells arranged in a plurality of columns;
first means for assisting writing to a first group of memory cells of the plurality of memory cells, the first means including write and boost logic; and
second means for assisting writing to a second group of memory cells of the plurality of memory cells, the second means including write and boost logic,
wherein the first group and the second group of memory cells share a pair of bitlines routed through the memory array, wherein the first means for assisting writing and the second means for assisting writing are located on opposite sides of the memory array and wherein the first means and the second means are operatively coupled to the pair of bitlines, the first write assist circuit configured to boost voltages applied to the pair of bitlines to write to one of the plurality of memory cells from the first group and the second write assist circuit configured to boost voltages applied to the pair of bitlines to write to one of the plurality of memory cells from the second group.

14. The apparatus of claim 13 , wherein a first edge cell is between the first means for assisting writing and the memory array and a second edge cell is between the second means for assisting writing and the memory array.

15. The apparatus of claim 13 , wherein one or more of the memory cells from the first group and one or more of the memory cells from the second group are arranged in a column.

16. The apparatus of claim 15 , further comprising a bitline operatively coupled to each of the memory cells in the column.

Assignees

• Qualcomm Inc

Inventors

• Raj Pradeep
• Gupta Sharad Kumar
• Sahu Rahul
• Holla Vakwadi Lakshmikantha

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title