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SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
US8971097B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8971097-B2 |
| Application number | US-201213976326-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 27, 2012 |
| Priority date | Dec 27, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
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We claim: 1. An apparatus comprising: a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. 2. The apparatus of claim 1 , wherein the global wri…
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Physics · mapped topic
Physics · mapped topic
- G11C5/066Primary
Physics · mapped topic
- G11C11/419Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8971097B2 cover?
- Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexer…
- Who is the assignee on this patent?
- Ngo Hieu T, Cummings Daniel J, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C5/066. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).