Processing system with interspersed processors with multi-layer interconnection

Patent metadata

Field	Value
Publication number	US-9720867-B2
Application number	US-201615219095-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Nov 21, 2012
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of processors;
a plurality of configurable communication elements coupled to the plurality of processors in an interspersed arrangement;
wherein each configurable communication element included in a subset of the plurality of configurable communication elements is coupled to at least one processor of a subset of the plurality of processors, and is configured to selectively protect at least some communication messages;
wherein to selectively protect the at least some communication messages, each configurable communication element of the subset of the plurality of configurable communication elements is further configured to:
receive a message from a particular processor excluded from the subset of the plurality of processors; and
relay the message to another processor excluded from the subset of the plurality of processors dependent upon configuration information.

2. The apparatus of claim 1 , wherein each configurable communication element of the subset of configurable communication elements is further configured to receive the configuration information via a serial bus.

3. The apparatus of claim 1 , further comprising a plurality of memories, wherein each memory of the plurality of memories is coupled to a respective processor of the plurality of processors.

4. The apparatus of claim 3 , wherein to relay the message to the another processors, each configurable communication element of the plurality of configurable communication elements is further configured to limit access to each processor included in the subset of the plurality of processors and limit access to a subset of the plurality of memories, wherein each memory of the subset of the plurality of memories is coupled to respective processor of the subset of the plurality of processor.

5. The apparatus of claim 1 , wherein each configurable communication element of the plurality of configurable communication elements includes a routing engine, and wherein each routing engine includes a register configured to store at least a portion of the configuration information.

6. The apparatus of claim 1 , wherein each configurable communication element of the plurality of configurable communication elements is coupled to a first communication layer and a second communication layer, and wherein to relay the message to the another processor, each configurable communication element of the subset of the plurality of configurable communication elements is further configured to relay the message on the first communication layer and restrict access of the message to the second communication layer.

7. A method of operating a multiprocessors system, comprising:
designating a subset of a plurality of processors to be used for executing a protected program, wherein a plurality of configurable communication elements is coupled to the plurality of processors in an interspersed arrangement;
executing the protected program using the subset of the plurality of processors; and
transmitting a message from a first processor of the plurality of processors to a second processor of the plurality of processors, wherein the message is relayed through at least one configurable communication element of the plurality of configurable communication elements, wherein the at least one configurable communication element is coupled to at least one processor included in the subset of the plurality of processors; and wherein the first processor and the second processor are excluded from the subset of the plurality of processors.

8. The method of claim 7 , wherein designating the subset of the plurality of processors includes disabling communication pathways at a boundary between the subset of the plurality of processors and remaining processors of the plurality of processors.

9. The method of claim 8 , wherein disabling the communication pathways at the boundary includes transmitting, via a serial bus, configuration information to one or more configurable communication elements, wherein each of the one or more configurable communication elements is coupled to at least one processor of the subset of the plurality of processors.

10. The method of claim 7 , wherein each processor of the plurality of processors is coupled to respective memory of a plurality of memories, and wherein transmitting the message includes limiting access to each processor included in the subset of the plurality of processors and limiting access to a subset of the plurality of memories, wherein each memory of the subset of the plurality of memories is coupled to respective processor of the subset of the plurality of processors.

11. The method of claim 7 , wherein each configurable communication element of the plurality of configurable communication elements includes a routing engine, and wherein designating the subset of the plurality of processors includes storing configuration information in a configuration register included in the routing engine of each configurable communication element included in a subset of the plurality of configurable communication elements.

12. The method of claim 7 , wherein each configurable communication element of the plurality of configurable communication elements is coupled to a first communication layer and a second communication layer, and wherein transmitting the message includes transmitting the message on the first communication layer and restricting access of the message to the second communication layer.

13. The method of claim 7 , further comprising, relaying, by the plurality of configurable communication elements, a plurality of messages using a plurality of communication layers, and designating a subset of a plurality of configurable communication elements, wherein designative the subset of the plurality of configurable communication elements includes restricting access, for a particular configurable communication element of the subset of the plurality of configurable communication elements, to at least one of the plurality of communication layers.

14. The method of claim 12 , further comprising transmitting a secure message using the second communication layer from a third processor to a fourth processor, wherein the third processor and the fourth processor are included in the subset of the plurality of processors.

15. A system, comprising:
a plurality of processors,
a plurality of memories interspersed among the plurality of processors, wherein each memory is coupled to a subset of the plurality of processors; and
a plurality of routing engines, wherein each routing engine of the plurality of routing engines is coupled to a respective one of the plurality of memories, a first subset of a plurality of links, and a second subset of the plurality of links;
wherein each link of the first subset of the plurality of links is coupled to a respective one of a first subset of the plurality of routing engines;
wherein each link of the second subset of the plurality of links is coupled to a respective one of a second subset of the plurality of routing engines;
wherein a subset of the plurality of processors is configured to execute a protected program;
wherein each routing engine included in a subset of the plurality of routing engines is coupled to at least one processor of the subset of the plurality of processors, and is configured to:
receive a message from a particular processor excluded from the subset of the plurality of processors; and
relay the message to another processor excluded from the subset of the plurality of processors dependent upon configuration information.

16. The system of claim 15 , w

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R
• Solka Michael B

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F15/8038

  Associative processors · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title