Transaction-level testing of memory I/O and memory device

Patent metadata

Field	Value
Publication number	US-8996934-B2
Application number	US-201213631961-A
Country	US
Kind code	B2
Filing date	Sep 29, 2012
Priority date	Sep 29, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

First claim

What is claimed is:

1. A method comprising:
receiving, by a test engine, a memory test software command indicating a test to perform on a memory device;
generating, by the test engine, in response to receiving the software command, a memory access transaction to perform the memory test; and
passing the memory access transaction from the test engine to a memory controller device, bypassing a memory address decoder associated with the memory controller device, to cause the memor…

Assignees

• Intel Corp

Inventors

• Mozak Christopher P
• Schoenborn Theodore Z
• Shehadi James M

Classifications

• G11C2029/5602

  Physics · mapped topic

• G11C29/56 Primary

  Physics · mapped topic

• G11C29/08 Primary

  Physics · mapped topic