Digital measurement of DAC switching mismatch error

Patent metadata

Field	Value
Publication number	US-9716509-B2
Application number	US-201615360617-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Dec 15, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

First claim

What is claimed is:

1. A method for measuring switching mismatch error, comprising:
applying a fixed frequency square wave signal to an input of an element under test of a feedback digital to analog converter (DAC), wherein the feedback DAC has an output which is coupled to an analog input of an analog to digital converter (ADC) having a feedback loop configuration and an input which is coupled to a digital output of the ADC; and
measuring a switching mismatch error of the element under test of feedback digital to analog converter based on the fixed frequency square wave and the digital output of the ADC.

2. The method of claim 1 , further comprising:
shorting the analog input to the ADC to ground.

3. The method of claim 1 , wherein the measuring of the switching mismatch error comprises accumulating samples of the digital output of the ADC.

4. The method of claim 1 , wherein:
the measuring of the switching mismatch error comprises dividing a sum of samples of the digital output of the ADC by a number of transitions; and
the number of transitions is a frequency of the fixed frequency square wave multiplied by a period of time the fixed frequency square wave is applied to the input of the element under test.

5. The method of claim 1 , further comprising:
while the fixed frequency square wave signal is applied to the input of the element under test, the digital output of the ADC is applied to other elements of the feedback DAC.

6. The method of claim 1 , further comprising:
forcing one or more other elements of the feedback DAC to output a value, wherein the value is selected such that the element under test does not toggle when the switching mismatch error is being measured.

7. A circuit for measuring switching mismatch, comprising:
a measurement block for accumulating samples of a digital output of an analog to digital converter (ADC) having a feedback digital to analog converter (DAC) when a fixed frequency square wave is driving an input of an element in the feedback DAC; and
a divide block for determining switching mismatch error based on accumulated samples of the digital output and a number of transitions introduced to the input of the element under test by the fixed frequency square wave.

8. The circuit of claim 7 , wherein:
the number of transitions is a frequency of the fixed frequency square wave multiplied by a period of time the fixed frequency square wave is applied to the input of the element under test.

9. The circuit of claim 7 , further comprising:
a buffer for storing samples of the digital output of the ADC collected when the fixed frequency square wave is applied to the input of the element under test.

10. The circuit of claim 7 , further comprising:
selection circuitry for applying either the fixed frequency square wave or a corresponding part of the digital output of the ADC to the input of the element under test.

11. The circuit of claim 7 , further comprising:
a switch for shorting an analog input to the ADC to ground.

12. The circuit of claim 7 , further comprising:
a square wave generator for generating the fixed frequency square wave.

13. The circuit of claim 7 , wherein:
the fixed frequency square wave has a frequency of a sampling frequency of the feedback DAC divided by four.

14. The circuit of claim 7 , wherein:
the feedback DAC comprises DAC element(s) which are forced to output a value, wherein the value is selected such that the element under test does not toggle when the switching mismatch error is being measured.

15. An apparatus comprising:
a quantizer for digitizing an analog input and generating a digital output;
a feedback digital to analog converter (DAC) receiving the digital output as input and providing a feedback signal to the analog input;
means for applying a fixed frequency square wave signal to a DAC element under test of the feedback DAC while a remainder of DAC elements of the feedback DAC receives the digital output;
means for measuring the digital output; and
means for determining switching mismatch error from the fixed frequency square wave signal and the digital output.

16. The apparatus of claim 15 , wherein:
the feedback DAC comprises means for forcing DAC element(s) to output a value, wherein the value is selected such that the DAC element under test does not toggle when the switching mismatch error is being measured.

17. The apparatus of claim 15 , wherein means for determining switching mismatch error comprises:
means for determining a DC component in the digital output caused by transitions of the fixed frequency square wave signal when the fixed frequency square wave signal is being applied.

18. The apparatus of claim 17 , wherein means for determining switching mismatch error comprises:
means for determining the switching mismatch error based on the DC component and a number of the transitions, the number of transitions being a frequency of the fixed frequency square wave signal multiplied by a period of time the fixed frequency square wave signal is applied to the input of the DAC element under test.

19. The apparatus of claim 15 , wherein the apparatus is a pipeline analog-to-digital converter.

20. The apparatus of claim 15 , wherein the apparatus is a continuous-time delta-sigma modulator in a multi-stage delta sigma analog-to-digital converter.

Assignees

• Analog Devices Inc

Inventors

• Zhao Jialin

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M3/378

  Testing · CPC title