Method of manufacturing n-p-n nitride-semiconductor light-emitting device, and n-p-n nitride-semiconductor light-emitting device

US9716209B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9716209-B2
Application numberUS-201615244763-A
CountryUS
Kind codeB2
Filing dateAug 23, 2016
Priority dateFeb 26, 2014
Publication dateJul 25, 2017
Grant dateJul 25, 2017

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Abstract

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This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region (A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer. In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer, and a p-type GaN crystal layer with low electric resistance can be obtained.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of manufacturing a nitride-semiconductor light-emitting device, the method comprising: stacking a buried tunnel junction layer above a first p-type nitrided compound layer that is stacked above an active layer, the buried tunnel junction layer is formed as a second p-type nitrided compound layer and a first n-type compound layer stacked in this order; removing the buried tunnel junction layer while a region through which the current flows to the active layer is being left; wherein the removing of the buried tunnel junction layer forms a first region of the first p-type nitrided compound layer with an exposed surface and a second region of the first p-type nitrided compound layer directly under the buried tunnel junction layer which is left; performing p-type activation on the second region of the first p-type nitrided compound layer using the exposed surface of the first p-type nitrided compound layer in the first region; and stacking a second n-type nitrided compound layer above the buried tunnel junction layer and the first p-type nitrided compound layer to bury the buried tunnel junction layer. 2. The method according to claim 1 , further comprising, between the performing p-type activation on the second region of the first p-type nitrided compound layer and the stacking the second n-type nitrided compound layer, performing p-type deactivation on the first region of the first p-type nitrided compound layer. 3. The method according to claim 2 , wherein the performing p-type activation on the second region of the first p-type nitrided compound layer includes first thermal annealing, the performing p-type deactivation on the first region of the first p-type nitrided compound layer includes second thermal annealing, and the first thermal annealing is performed under conditions including a higher treatment temperature or a longer treatment time or both than the second thermal annealing. 4. The method according to claim 1 , wherein in the stacking of the second n-type nitrided compound layer, hydrogen atoms exist in atmosphere gas or a raw material. 5. The method according to claim 4 , wherein the hydrogen atoms in the atmosphere gas are fed by using hydrogen gas as carrier gas for transporting the raw material or by being produced by a chemical reaction of the raw material.

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What does patent US9716209B2 cover?
This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region (A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel jun…
Who is the assignee on this patent?
Univ Meijo, Melio Univ
What technology area does this patent fall under?
Primary CPC classification H01L33/04. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).