Transistor structure with improved unclamped inductive switching immunity

Patent metadata

Field	Value
Publication number	US-9716166-B2
Application number	US-201615093557-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Aug 21, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

First claim

What is claimed:

1. A method of fabricating a semiconductor device, said method comprising:
growing an epitaxial layer over a doped substrate layer, said epitaxial layer and said doped substrate layer both of a first conductivity type, said epitaxial layer comprising a source region and a drain region that are both of a second conductivity type, said epitaxial layer further comprising a body structure of said first conductivity type;
forming a gate structure above said epitaxial layer;
forming an electrically conductive trench-like feed-through element that passes through said epitaxial layer and contacts said substrate layer and said source region; and
forming a first tub region of said first conductivity type under said source region, and adjacent laterally to and in contact with said body structure, wherein said first tub region is in contact with said trench-like feed-through element.

2. The method of claim 1 , further comprising:
forming a second tub region at least partially below said first tub region.

3. The method of claim 2 , wherein said body structure is less doped than said first tub region and wherein said second tub region is less doped than said first tub region.

4. The method of claim 1 , further comprising:
forming a clamp region of said first conductivity type under said drain region.

5. The method of claim 4 , wherein said drain region comprises:
a first doped region accessible to a drain contact; and
a second doped region located at least partially under said first region in said epitaxial layer, wherein said second doped region is less doped than said first doped region and wherein said second doped region separates said first doped region and said clamp region.

6. The method of claim 5 , wherein said clamp region is coarsely aligned with an edge of said first doped region.

7. The method of claim 5 , wherein said clamp region is coarsely aligned within an edge of said second doped region.

8. A method of fabricating a semiconductor transistor structure, said method comprising:
forming an epitaxial layer adjacent to a substrate of a first conductivity type;
forming a gate structure located above said epitaxial layer,
forming a drain region of a second conductivity type within said epitaxial layer;
forming a source region of said second conductivity type within said epitaxial layer;
forming a body structure of said first conductivity type within said epitaxial layer and at least partially under said gate structure and extending laterally under said source region;
forming an electrically conductive trench-like feed-through element that passes through said epitaxial layer and contacts said substrate and passes through and contacts said source region; and
forming a first tub region of said first conductivity type under said source region and adjacent laterally to and in contact with said body structure and in contact with said trench-like feed-through element.

9. The method of claim 8 , wherein said body structure is less doped than said first tub region.

10. The method of claim 8 , further comprising:
forming a second tub region formed at least partially below said first tub region, wherein said second tub region is less doped than said first tub region.

11. The method of claim 8 , wherein said forming said drain region comprises:
forming a first region accessible to a drain contact and spaced apart from said gate structure; and
forming a second region lightly doped and located at least partially under said first region within said epitaxial layer, wherein said second region extends to at least partially under said gate structure, wherein said second region is less doped than said first region, wherein said second region is coarsely aligned with an edge of said gate structure.

12. The method of claim 8 , wherein said source region is coarsely aligned with an edge of said gate structure.

13. The method of claim 8 , further comprising:
forming a clamp region of said first conductivity type under said drain region.

14. A method for fabricating a semiconductor transistor structure, said method comprising:
providing a substrate of a first conductivity type;
forming an epitaxial layer adjacent to said substrate, wherein said epitaxial layer comprises said first conductivity type;
forming a gate structure located above said epitaxial layer;
forming a drain region within said epitaxial layer, wherein said drain region comprises a second conductivity type;
forming a source region within said epitaxial layer, wherein said source region comprises said second conductivity type, wherein a channel is formed in said epitaxial layer between said source region and said drain region, wherein said channel is located at least partially below said gate structure;
forming a body structure of said first conductivity type within said epitaxial layer, wherein said body structure is at least partially formed under said gate structure and extends laterally under said source region;
forming a tub region under said source region and adjacent laterally to and in contact with said body structure, wherein said tub region comprises said first conductivity type; and
forming an electrically conductive trench-like feed-through element that passes through said epitaxial layer and contacts said first conductivity type substrate and passes through and contacts said second conductivity type source region; and passes through and contacts said tub region of said first conductivity type formed under said source region, and adjacent laterally to and in contact with said body structure.

15. The method of claim 14 , wherein said forming a tub region further comprises:
forming a first tub region at least partially below said source region and adjacent laterally to and in contact with said body structure, wherein said body structure is less doped than said first tub region.

16. The method of claim 15 , wherein said forming a tub region further comprises:
forming a second tub region at least partially below said first tub region, wherein said second tub region is less doped than said first tub region.

17. The method of claim 14 , wherein said forming a drain region comprises:
forming a first region located under a drain contact and spaced apart from said gate structure; and
forming a second region lightly doped and located under said first region within said epitaxial layer, wherein said second region extends to at least partially under said gate structure, wherein said second region is less doped than said first region.

18. The method of claim 17 , further comprising:
forming a clamp region of said first conductivity type located under said first region such that said second region separates said first region and said clamp region.

19. The method of claim 18 , wherein said forming a clamp region further comprises:
extending said clamp region towards said source region, such that an edge of said clamp region distal from said drain region lies falls within an area in said epitaxial layer defined by a coarse alignment with a first edge of said first region and a second coarse alignment with a second edge of said lightly doped second region.

20. The method of claim 14 , wherein said first conductivity type comprises a p-type, and wherein said second conductivity type comprises an n-type.

Assignees

• Vishay Siliconix

Inventors

• Zhang Wenjie
• Bobde Madhur
• Chen Qufei
• Terrill Kyle

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/0623

  Electricity · mapped topic

• H01L29/66712

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/41766

  Electricity · mapped topic