Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9716162-B2
Application number	US-201514697829-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Jul 28, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an active pattern;
a gate electrode crossing the active pattern;
gate spacer structures at both sidewalls of the gate electrode;
a gate capping pattern on the gate electrode, the gate capping pattern having an upper surface that is substantially flat; and
an insulating layer covering a top surface of the gate capping pattern from a top and covering at least one of two opposing sides of the gate capping pattern from at least one side, the gate capping pattern having an etch selectivity with respect to the insulating layer,
wherein the gate capping pattern has a width larger than that of the gate electrode,
the gate capping pattern includes extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode, and
the gate spacer structures and the gate capping pattern are formed of different materials from each other.

2. The device of claim 1 , further comprising:
a gate dielectric layer interposed between the gate electrode and the substrate; and
epitaxial patterns provided on the active pattern at both sides of the gate electrode.

3. The device of claim 2 , further comprising:
contact plugs provided on the substrate at both sides of the gate electrode and connected to the epitaxial patterns, respectively,
wherein each of the contact plugs contacts at least a portion of the gate capping pattern.

4. The device of claim 2 , further comprising:
an active fin extending upward from a top surface of the active pattern,
wherein the gate electrode is disposed to cross the active fin, and
the gate dielectric layer is disposed to extend along a bottom surface of the gate electrode and cover top and side surfaces of the active fin.

5. The device of claim 4 , wherein the active fin is provided between the epitaxial patterns and below the gate electrode, and
wherein the gate electrode comprises first portions facing both sidewalls of the active fin and a second portion provided on the active fin to connect the first portions to each other.

6. The device of claim 1 , wherein the gate capping pattern includes a seam formed at an upper portion thereof.

7. The device of claim 1 , wherein the width of the gate capping pattern increases in a direction away from the substrate.

8. The device of claim 7 , wherein at least one of the extended portions has a bottom surface that is in direct contact with a top surface of the substrate.

9. The device of claim 1 ,
wherein the extended portions of the gate capping pattern cover top surfaces of the gate spacer structures, respectively, and the top surfaces of the gate spacer structures are at a lower level than a top surface of the gate electrode.

10. The device of claim 1 , wherein the gate capping pattern has a relatively higher dielectric constant than the insulating layer.

11. The device of claim 1 , further comprising:
first and second contact plugs penetrating the insulating layer respectively at two sides of the gate electrodes, the first contact plug being in contact with at least a portion of the gate capping pattern and penetrating the insulating layer along a contour of the gate capping pattern, the second contact plug laterally spaced apart from the gate capping pattern and penetrating through the insulating layer.

12. A semiconductor device, comprising:
a conductive pattern on a substrate;
an interlayered insulating layer surrounding the conductive pattern; and
a capping pattern on the conductive pattern,
wherein the capping pattern comprises extended portions extending toward the substrate and covering both sidewalls of the conductive pattern,
the capping pattern is in contact with the interlayered insulating layer, and
the capping pattern has a width monotonously increasing in a direction away from the substrate such that the width of the capping pattern at a top thereof is wider than the width of the capping pattern at an interface between the conductive pattern and the capping pattern.

13. The semiconductor device of claim 12 , wherein the capping pattern directly cover both sidewalls of the conductive pattern.

14. A semiconductor device, comprising:
a substrate including an active pattern;
a gate electrode crossing the active pattern;
spacer structures on two opposite sidewalls of the gate electrode; and
a gate capping pattern on the gate electrode,
wherein the gate capping pattern has an upper surface that is substantially flat and a width of the gate capping pattern is larger than that of the gate electrode,
the gate capping pattern at least partially covers the two sidewalls of the gate electrode,
the gate capping pattern covers top surfaces of the spacer structures, and interfaces between the gate capping pattern and the spacer structures are at a lower level than a top surface of the gate electrode, and
the spacer structures and the gate capping pattern are formed of different materials from each other.

15. The device of claim 14 , wherein the width of the gate capping pattern increases in a direction away from the substrate.

16. The device of claim 14 , further comprising:
a gate dielectric layer interposed between the gate electrode and the substrate.

17. The device of claim 16 , further comprising:
epitaxial patterns on the active pattern at both sides of the gate electrode, respectively.

18. The device of claim 17 , further comprising:
contact plugs on the substrate at both sides of the gate electrode respectively, the contact plugs connected to the epitaxial patterns, respectively,
wherein at least one of the contact plugs contacts at least a portion of the gate capping pattern.

19. The device of claim 14 , wherein the gate capping pattern includes a seam at an upper portion thereof.

20. The semiconductor device of claim 14 , wherein the gate capping pattern at least partially directly covers the two sidewalls of the gate electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sangjine
• Baek Jae-Jik
• Song Myunggeun
• Yoon Boun
• Choi Sukhun
• Han Jeongnam

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L29/66636

  Electricity · mapped topic